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dual, 12-/14-/16-bit,1 gsps digital-to-analog converters ad9776a/ad9778a/AD9779A rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2008 analog devices, inc. all rights reserved. features low power: 1.0 w @ 1 gsps, 600 mw @ 500 msps, full operating conditions single carrier w-cdma aclr = 80 dbc @ 80 mhz if analog output: adjustable 8.7 ma to 31.7 ma, r l = 25 to 50 novel 2, 4, and 8 interpolator/coarse complex modulator allows carrier placement anywhere in dac bandwidth auxiliary dacs allow control of external vga and offset control multiple chip synchronization interface high performance, low noise pll clock multiplier digital inverse sinc filter 100-lead, exposed paddle tqfp applications wireless infrastructure w-cdma, cdma2000, td-scdma, wimax, gsm, lte digital high or low if synthesis internal digital upconversion capability transmit diversity wideband communications: lmds/mmds, point-to-point general description the ad9776a/ad9778a/AD9779A are dual, 12-/14-/16-bit, high dynamic range digital-to-analog converters (dacs) that provide a sample rate of 1 gsps, permitting a multicarrier generation up to the nyquist frequency. they include features optimized for direct conversion transmission applications, including complex digital modulation and gain and offset compensation. the dac outputs are optimized to interface seamlessly with analog quadrature modulators such as the adl537x fmod series from analog devices, inc. a 3-wire interface provides for programming/readback of many internal parameters. full-scale output current can be programmed over a range of 10 ma to 30 ma. the devices are manufactured on an advanced 0.18 m cmos process and operate on 1.8 v and 3.3 v supplies for a total power consumption of 1.0 w. they are enclosed in a 100-lead thin quad flat package (tqfp). product highlights 1. ultralow noise and intermodulation distortion (imd) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. 2. a proprietary dac output switching technique enhances dynamic performance. 3. the current outputs are easily configured for various single-ended or differential circuit topologies. 4. cmos data input interface with adjustable setup and hold. 5. novel 2, 4, and 8 interpolator/coarse complex modulator allows carrier placement anywhere in dac bandwidth. typical signal chain fpga/asic/dsp dc complex i and q dc lo quadrature modulator/ mixer/ amplifier i dac q dac digital interpolation filters ad9776a/ad9778a/AD9779A post dac analog filter a 0 6452-114 figure 1.
ad9776a/ad9778a/AD9779A rev. b | page 2 of 56 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? typical signal chain ......................................................................... 1 ? revision history ............................................................................... 3 ? functional block diagram .............................................................. 4 ? specifications ..................................................................................... 5 ? dc specifications ......................................................................... 5 ? digital specifications ................................................................... 6 ? digital input data timing specifications ................................. 7 ? ac specifications .......................................................................... 8 ? absolute maximum ratings ............................................................ 9 ? thermal resistance ...................................................................... 9 ? esd caution .................................................................................. 9 ? pin configurations and function descriptions ......................... 10 ? typical performance characteristics ........................................... 16 ? terminology .................................................................................... 24 ? theory of operation ...................................................................... 25 ? differences between ad9776/ad9778/ ad9779 and ad9776a/ad9778a/AD9779A............................................... 25 ? 3-wire interface .............................................................................. 26 ? general operation of the serial interface ............................... 26 ? instruction byte .......................................................................... 26 ? serial interface port pin descriptions ..................................... 27 ? msb/lsb transfers..................................................................... 27 ? 3-wire interface register map ...................................................... 28 ? interpolation filter architecture .................................................. 33 ? interpolation filter bandwidth limits .................................... 37 ? inverse sinc filter ....................................................................... 38 ? sourcing the dac sample clock ................................................. 39 ? direct clocking .......................................................................... 39 ? clock multiplication .................................................................. 39 ? driving the refclk input ....................................................... 42 ? full-scale current generation ..................................................... 43 ? internal reference ...................................................................... 43 ? gain and offset correction .......................................................... 44 ? i/q channel gain matching ..................................................... 44 ? auxiliary dac operation ......................................................... 44 ? lo feedthrough compensation .............................................. 45 ? results of gain and offset correction .................................... 45 ? input data ports ............................................................................. 46 ? single port mode ........................................................................ 46 ? dual port mode .......................................................................... 46 ? input data referenced to dataclk ...................................... 46 ? input data referenced to refclk ......................................... 47 ? optimizing the data input timing .......................................... 48 ? device synchronization ................................................................. 49 ? synchronization logic overview ............................................. 49 ? synchronizing devices to a system clock .............................. 50 ? interrupt request operation .................................................... 50 ? power dissipation ........................................................................... 51 ? power-down and sleep modes................................................. 52 ? evaluation board overview .......................................................... 53 ? evaluation board operation ..................................................... 53 ? outline dimensions ....................................................................... 55 ? ordering guide .......................................................................... 55 ?
ad9776a/ad9778a/AD9779A rev. b | page 3 of 56 revision history 9/08rev. a to rev. b changed serial peripheral interface (spi) to 3-wire interface throughout ................................................................................... 1 change to features section .............................................................. 1 change to applications section ...................................................... 1 changes to integral nonlinearity (inl) parameter, table 1 ....... 5 changes to dac clock input (refclk+, refclk?) parameter, table 2 ........................................................................ 6 changes to input data parameter, table 3 ..................................... 7 changes to hold time parameters, table 3 ................................... 7 added 3-wire interface parameter, table 3................................... 7 added reset parameter, table 3 ...................................................... 7 changes to endnotes, table 3 .......................................................... 7 added exposed pad notation to figure 3, changes to table 7 ...... 10 added exposed pad notation to figure 4, changes to table 8 ...... 12 added exposed pad notation to figure 5, changes to table 9 ...... 14 changes to dataclk delay range section .............................. 25 changes to version register section ............................................ 25 changes to table 10 ........................................................................ 25 changes to table 12 ........................................................................ 26 changes to table 13 ........................................................................ 28 changes to table 14 ........................................................................ 29 changes to interpolation filter architecture section ................ 33 changes to figure 60 ...................................................................... 34 changes to table 19 ........................................................................ 36 changes to interpolation filter bandwidth limits section ....... 37 changes to figure 70 ...................................................................... 37 added digital modulation section ............................................... 37 added table 20 and table 21; renumbered sequentially .......... 38 added inverse sinc filter section ................................................. 38 added figure 71; renumbered sequentially ............................... 38 changes to clock multiplication section .................................... 39 changes to figure 72 ...................................................................... 39 changes to configuring the pll band select value section .... 39 changes to configuring the pll band select with temperature sensing section ........................................................................... 41 changes to known temperature calibration with memory section ......................................................................................... 41 changes to set-and-forget device option section .................... 41 added table 26 ................................................................................ 41 changes to internal reference section......................................... 43 changed transmit path gain and offset correction heading to gain and offset correction ...................................................... 44 changes to i/q channel gain matching section ....................... 44 changes to auxiliary dac operation section ........................... 44 replaced figure 79 .......................................................................... 45 deleted figure 79; renumbered sequentially ............................. 41 changes to lo feedthrough compensation section ................. 45 changes to table 28 ........................................................................ 47 changes to optimizing the data input timing section ............ 48 change to synchronization logic overview section ................. 49 changes to figure 88 ...................................................................... 49 changes to figure 101 .................................................................... 53 deleted using the adl5372 quadrature modulator section and figure 104 .................................................................................... 51 deleted evaluation board schematics section and figure 105; renumbered sequentially ......................................................... 52 deleted figure 106 .......................................................................... 53 deleted figure 107 .......................................................................... 54 deleted figure 108 .......................................................................... 55 deleted figure 109 .......................................................................... 56 deleted figure 110 .......................................................................... 57 deleted figure 111 .......................................................................... 58 deleted figure 112 .......................................................................... 59 updated outline dimensions ........................................................ 60 3/08rev. 0 to rev. a changes to features .......................................................................... 1 added note 2 ..................................................................................... 4 changes to table 2 ............................................................................ 5 changes to table 3 ............................................................................ 6 changes to thermal resistance section ........................................ 7 inserted table 6 ................................................................................. 8 changes to pin 39 description, table 7 ......................................... 9 changes to pin 39 description, table 8 ....................................... 10 changes to pin 39 description, table 9 ....................................... 12 changes to theory of operation section .................................... 23 changes to table 10 ........................................................................ 23 changes to table 13 ........................................................................ 26 changes to table 14 ........................................................................ 27 changes to interpolation filter architecture section ................ 33 replaced sourcing the dac sample clock section ................... 36 replaced transmit path gain and offset correction section ........ 40 replaced input data ports section ............................................... 42 replaced device synchronization section .................................. 45 deleted figure 112 to figure 117 .................................................. 58 8/07revision 0: initial version
ad9776a/ad9778a/AD9779A rev. b | page 4 of 56 functional block diagram 10 10 10 10 clock generation/distribution data assembler digital controller 2 2 sinc^-1 clock multiplier 2/4/8 16-bit i dac refclk+ refclk? out1_p out1_n aux1_p aux1_n aux2_p aux2_n out2_p out2_n gain gain gain gain 16-bit q dac 2 sinc^-1 i latch delay line q latch p2d[15:0] p1d[15:0] sync_o sync_i dataclk 2 2 2 n f dac /8 n = 0, 1, 2 ... 7 power-on reset sdo sdio scl k csb serial peripheral interface complex modulator reference and bias vref i120 delay line AD9779A 0 6452-001 figure 2. AD9779A functional block diagram
ad9776a/ad9778a/AD9779A rev. b | page 5 of 56 specifications dc specifications t min to t max , avdd33 = 3.3 v, dvdd33 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i outfs = 20 ma, maximum sample rate, unless otherwise noted. table 1. ad9776a ad9778a AD9779A parameter min typ max min typ max min typ max unit resolution 12 14 16 bits accuracy differential nonlinearity (dnl) 0.1 0.65 2.1 lsb integral nonlinearity (inl) 0.86 1.5 6.0 lsb main dac outputs offset error ?0.001 0 +0.001 ?0.001 0 +0.001 ?0.001 0 +0.001 % fsr gain error (with internal reference) 2 2 2 % fsr full-scale output current 1 8.66 20.2 31.66 8.66 20.2 31.66 8.66 20.2 31.66 ma output compliance range ?1.0 +1 .0 ?1.0 +1.0 ?1.0 +1.0 v output resistance 10 10 10 m gain dac monotonicity guaranteed guaranteed guaranteed main dac temperature drift offset 0.04 0.04 0.04 ppm/c gain 100 100 100 ppm/c reference voltage 30 30 30 ppm/c auxiliary dac outputs resolution 10 10 10 bits full-scale output current 1 ?1.998 +1.998 ?1.998 +1.998 ?1.998 +1.998 ma output compliance range (source) 0 1.6 0 1.6 0 1.6 v output compliance range (sink) 0.8 1.6 0.8 1.6 0.8 1.6 v output resistance 1 1 1 m auxiliary dac monotonicity gu aranteed guaranteed guaranteed reference internal reference voltage 1.2 1.2 1.2 v output resistance 5 5 5 k analog supply voltages avdd33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 v cvdd18 1.70 1.8 2.05 1.70 1.8 2.05 1.70 1.8 2.05 v digital supply voltages dvdd33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 v dvdd18 1.70 1.8 2.05 1.70 1.8 2.05 1.70 1.8 2.05 v power consumption 2 1 mode, f dac = 100 msps, if = 1 mhz 250 300 250 300 250 300 mw 2 mode, f dac = 320 msps, if = 16 mhz, pll off 498 498 498 mw 2 mode, f dac = 320 msps, if = 16 mhz, pll on 588 588 588 mw 4 mode, f dac /4 modulation, f dac = 500 msps, if = 137.5 mhz, q dac off 572 572 572 mw 8 mode, f dac /4 modulation, f dac = 1 gsps, if = 262.5 mhz 980 980 980 mw power-down mode 2.5 9.8 2.5 9.8 2.5 9.8 mw power supply rejection ratio, avdd33 ?0.3 +0.3 ?0.3 +0.3 ?0.3 +0.3 % fsr/v operating range ?40 +25 +85 ?40 +25 +85 ?40 +25 +85 c 1 based on a 10 k external resistor. 2 see the power dissipation section for more details.
ad9776a/ad9778a/AD9779A rev. b | page 6 of 56 digital specifications t min to t max , avdd33 = 3.3 v, dvdd33 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i outfs = 20 ma, maximum sample rate, unless otherwise noted. lvds driver and receiver are compliant to the ieee-1596 reduced range link, unless otherwise noted. table 2. parameter conditions min typ max unit cmos input logic level input v in logic high 2.0 v input v in logic low 0.8 v maximum input data rate at interpolation 1 300 msps 2 250 msps 4 200 msps 8 dvdd18, cvdd18 = 1.8 v 5% 112.5 msps dvdd18, cvdd18 = 1.9 v 5% 125 msps dvdd18, cvdd18 = 2.0 v 2% 137.5 msps cmos output logic level (dataclk, pin 37) 1 output v out logic high 2.4 v output v out logic low 0.4 v dataclk output duty cycle at 250 mhz, into 5 pf load 40 50 60 % lvds receiver inputs (sync_i+, sync_i?) sync_i+ = v ia , sync_i? = v ib input voltage range, v ia or v ib 825 1575 mv input differential threshold, v idth ?100 +100 mv input differential hysteresis, v idthh ? v idthl 20 mv receiver differential input impedance, r in 80 120 lvds input rate additional limits on f sync_i apply; see description of register 0x05, bits[3:1], in table 14 250 msps setup time, sync_i to refclk 0.4 ns hold time, sync_i to refclk 0.55 ns lvds driver outputs (sync_o+, sync_o?) sync_o+ = v oa , sync_o? = v ob , 100 termination output voltage high, v oa or v ob 1375 mv output voltage low, v oa or v ob 1025 mv output differential voltage, |v od | 150 200 250 mv output offset voltage, v os 1150 1250 mv output impedance, r o single-ended 80 100 120 dac clock input (refclk+, refclk?) differential peak-to-peak voltage 400 800 2000 mv common-mode voltage 300 400 500 mv maximum clock rate dvdd18, cvdd18 = 1.8 v 5%, pll off 900 mhz dvdd18, cvdd18 = 1.9 v 5%, pll off 1000 mhz dvdd18, cvdd18 = 2.0 v 2%, pll off 1100 mhz dvdd18, cvdd18 = 2.0 v 2%, pll on 250 mhz 1 specification is at a dataclk frequency of 100 mhz into a 1 k load, with maximum drive capability of 8 ma. at higher speeds o r greater loads, best practice suggests using an external buffer for this signal.
ad9776a/ad9778a/AD9779A rev. b | page 7 of 56 digital input data timing specifications all modes, ?40c to +85c. table 3. parameter conditions min typ max unit input data 1 setup time input data to dataclk 3.0 ns hold time input data to dataclk ?0.05 ns setup time input data to refclk ?0.80 ns hold time input data to refclk 3.80 ns latency 1 interpolation with or without modulation 25 dacclk cycles 2 interpolation with or without modulation 70 dacclk cycles 4 interpolation with or without modulation 146 dacclk cycles 8 interpolation with or without modulation 297 dacclk cycles inverse sync 18 dacclk cycles 3-wire interface maximum clock rate (sclk) 40 mhz minimum pulse width high, t pwh 12.5 ns minimum pulse width low, t pwl 12.5 ns setup time, t ds sdio to sclk 2.8 ns hold time, t dh sdio to sclk 0.0 ns setup time, t ds csb to sclk 2.8 ns data valid, t dv sdo to sclk 2.0 ns power-up time 2 260 ms reset minimum pulse width, high 2 dacclk cycles 1 specified values are with pll disabled. t iming vs. temperature and data valid keep out windows (that is, the minimum amount of time valid data must be presented to the device to ensure proper sampling) are delineated in table 28. 2 measured from csb rising edge when register 0x00, bit 4, is written from 1 to 0 with the vref decoupling capacitor equal to 0. 1 f.
ad9776a/ad9778a/AD9779A rev. b | page 8 of 56 ac specifications t min to t max , avdd33 = 3.3 v, dvdd33 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i outfs = 20 ma, maximum sample rate, unless otherwise noted. table 4. ad9776a ad9778a AD9779A parameter min typ max min typ max min typ max unit spurious-free dynamic range (sfdr) f dac = 100 msps, f out = 20 mhz 82 82 82 dbc f dac = 200 msps, f out = 50 mhz 81 81 82 dbc f dac = 400 msps, f out = 70 mhz 80 80 80 dbc f dac = 800 msps, f out = 70 mhz 85 85 87 dbc two-tone intermodulation distortion (imd) f dac = 200 msps, f out = 50 mhz 87 87 91 dbc f dac = 400 msps, f out = 60 mhz 80 85 85 dbc f dac = 400 msps, f out = 80 mhz 75 81 81 dbc f dac = 800 msps, f out = 100 mhz 75 80 81 dbc noise spectral density (nsd), eight-tone, 500 khz tone spacing f dac = 200 msps, f out = 80 mhz ?152 ?155 ?158 dbm/hz f dac = 400 msps, f out = 80 mhz ?155 ?159 ?160 dbm/hz f dac = 800 msps, f out = 80 mhz ?157.5 ?160 ?161 dbm/hz w-cdma adjacent channel leakage ratio (aclr), single carrier f dac = 491.52 msps, f out = 100 mhz 76 78 79 dbc f dac = 491.52 msps, f out = 200 mhz 69 73 74 dbc w-cdma second adjacent channel leakage ratio (aclr), single carrier f dac = 491.52 msps, f out = 100 mhz 77.5 80 81 dbc f dac = 491.52 msps, f out = 200 mhz 76 78 78 dbc
ad9776a/ad9778a/AD9779A rev. b | page 9 of 56 absolute maximum ratings table 5. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter with respect to rating avdd33, dvdd33 agnd, dgnd, cgnd ?0.3 v to +3.6 v dvdd18, cvdd18 agnd, dgnd, cgnd ?0.3 v to +2.1 v agnd dgnd, cgnd ?0.3 v to +0.3 v dgnd agnd, cgnd ?0.3 v to +0.3 v cgnd agnd, dgnd ?0.3 v to +0.3 v i120, vref, iptat agnd ?0.3 v to avdd33 + 0.3 v out1_p, out1_n, out2_p, out2_n, aux1_p, aux1_n, aux2_p, aux2_n agnd ?1.0 v to avdd33 + 0.3 v p1d[15:0], p2d[15:0] dgnd ?0.3 v to dvdd33 + 0.3 v dataclk, txenable dgnd ?0.3 v to dvdd33 + 0.3 v refclk+, refclk? cgnd ?0.3 v to cvdd18 + 0.3 v reset, irq, pll_lock, sync_o+, sync_o?, sync_i+, sync_i?, csb, sclk, sdio, sdo dgnd ?0.3 v to dvdd33 + 0.3 v junction temperature +125c storage temperature range ?65c to +150c thermal resistance for optimal thermal performance, the exposed paddle (epad) should be soldered to the ground plane for the 100-lead, thermally enhanced tqfp package. typical ja and jc are specified for a 4-layer board in still air. airflow increases heat dissipation, effectively reducing ja . table 6. thermal resistance package type ja jb jc unit 100-lead tqfp epad soldered 19.1 12.4 7.1 c/w epad not soldered 27.4 c/w esd caution
ad9776a/ad9778a/AD9779A rev. b | page 10 of 56 pin configurations and function descriptions 74 vref 73 iptat 72 agnd 69 csb 70 reset 71 irq 75 i120 68 sclk 67 sdio 66 sdo 64 dgnd 63 sync_o+ 62 sync_o? 61 dvdd33 60 dvdd18 59 nc 58 nc 57 nc 56 nc 55 p2d0 54 dgnd 53 dvdd18 52 p2d1 51 p2d2 65 pll_lock pin 1 100 avdd33 99 agnd 98 avdd33 97 agnd 96 avdd33 95 agnd 94 agnd 93 out1_p 92 out1_n 91 agnd 90 aux1_p 89 aux1_n 88 agnd 87 aux2_n 86 aux2_p 85 agnd 84 out2_n 83 out2_p 82 agnd 81 agnd 80 avdd33 79 agnd 78 avdd33 77 agnd 76 avdd33 26 p1d4 27 p1d3 28 p1d2 29 p1d1 30 p1d0 31 nc 32 dgnd 33 dvdd18 34 nc 35 nc 36 nc 37 dataclk 38 dvdd33 39 txenable/iqselect 40 p2d11 41 p2d10 42 p2d9 43 dvdd18 44 dgnd 45 p2d8 46 p2d7 47 p2d6 48 p2d5 49 p2d4 50 p2d3 2 cvdd18 3 cgnd 4 cgnd 7 cgnd 6 refclk? 5 refclk+ 1 cvdd18 8 cgnd 9 cvdd18 10 cvdd18 12 agnd 13 sync_i+ 14 sync_i? 15 dgnd 16 dvdd18 17 p1d11 18 p1d10 19 p1d9 20 p1d8 21 p1d7 22 dgnd 23 dvdd18 24 p1d6 25 p1d5 11 cgnd ad9776a top view (not to scale) analog domain digital domain nc = no connect 06452-002 notes 1. for optim a l thermal performance, the exposed pad should be soldered to the ground plane for the 100-lead, therma l ly enhanced tqfp package. figure 3. ad9776a pin configuration table 7. ad9776a pin fu nction descriptions pin no. mnemonic description pin no. mnemonic description 1 cvdd18 1.8 v clock supply. 17 p1d11 port 1, data input d11 (msb). 2 cvdd18 1.8 v clock supply. 18 p1d10 port 1, data input d10. 3 cgnd clock ground. 19 p1d9 port 1, data input d9. 4 cgnd clock ground. 20 p1d8 port 1, data input d8. 5 refclk+ differential clock input. 21 p1d7 port 1, data input d7. 6 refclk? differential clock input. 22 dgnd digital ground. 7 cgnd clock ground. 23 dvdd18 1.8 v digital supply. 8 cgnd clock ground. 24 p1d6 port 1, data input d6. 9 cvdd18 1.8 v clock supply. 25 p1d5 port 1, data input d5. 10 cvdd18 1.8 v clock supply. 26 p1d4 port 1, data input d4. 11 cgnd clock ground. 27 p1d3 port 1, data input d3. 12 agnd analog ground. 28 p1d2 port 1, data input d2. 13 sync_i+ differential synchronization input. 29 p1d1 port 1, data input d1. 14 sync_i? differential synchronization input. 30 p1d0 port 1, data input d0 (lsb). 15 dgnd digital ground. 31 nc no connect. 16 dvdd18 1.8 v digital supply. 32 dgnd digital ground.
ad9776a/ad9778a/AD9779A rev. b | page 11 of 56 pin no. mnemonic description 33 dvdd18 1.8 v digital supply. 34 nc no connect. 35 nc no connect. 36 nc no connect. 37 dataclk data clock output. 38 dvdd33 3.3 v digital supply. 39 txenable/ iqselect transmit enable. in single port mode, this pin also functions as iqselect. 40 p2d11 port 2, data input d11 (msb). 41 p2d10 port 2, data input d10. 42 p2d9 port 2, data input d9. 43 dvdd18 1.8 v digital supply. 44 dgnd digital ground. 45 p2d8 port 2, data input d8. 46 p2d7 port 2, data input d7. 47 p2d6 port 2, data input d6. 48 p2d5 port 2, data input d5. 49 p2d4 port 2, data input d4. 50 p2d3 port 2, data input d3. 51 p2d2 port 2, data input d2. 52 p2d1 port 2, data input d1. 53 dvdd18 1.8 v digital supply. 54 dgnd digital ground. 55 p2d0 port 2, data input d0 (lsb). 56 nc no connect. 57 nc no connect. 58 nc no connect. 59 nc no connect. 60 dvdd18 1.8 v digital supply. 61 dvdd33 3.3 v digital supply. 62 sync_o? differential synchronization output. 63 sync_o+ differential synchronization output. 64 dgnd digital ground. 65 pll_lock pll lock indicator. 66 sdo 3-wire interface port data output. 67 sdio 3-wire interface port data input/output. 68 sclk 3-wire interface port clock. pin no. mnemonic description 69 csb 3-wire interface port chip select bar. 70 reset reset, active high. 71 irq interrupt request. 72 agnd analog ground. 73 iptat factory test pin. output current is proportional to absolute temperature, approximately 14 a at 25c with approximately 20 na/c slope. this pin should remain floating. 74 vref voltage reference output. 75 i120 120 a reference current. 76 avdd33 3.3 v analog supply. 77 agnd analog ground. 78 avdd33 3.3 v analog supply. 79 agnd analog ground. 80 avdd33 3.3 v analog supply. 81 agnd analog ground. 82 agnd analog ground. 83 out2_p differential dac current output, channel 2. 84 out2_n differential dac current output, channel 2. 85 agnd analog ground. 86 aux2_p auxiliary dac current output, channel 2. 87 aux2_n auxiliary dac current output, channel 2. 88 agnd analog ground. 89 aux1_n auxiliary dac current output, channel 1. 90 aux1_p auxiliary dac current output, channel 1. 91 agnd analog ground. 92 out1_n differential dac current output, channel 1. 93 out1_p differential dac current output, channel 1. 94 agnd analog ground. 95 agnd analog ground. 96 avdd33 3.3 v analog supply. 97 agnd analog ground. 98 avdd33 3.3 v analog supply. 99 agnd analog ground. 100 avdd33 3.3 v analog supply.
ad9776a/ad9778a/AD9779A rev. b | page 12 of 56 74 vref 73 iptat 72 agnd 69 csb 70 reset 71 irq 75 i120 68 sclk 67 sdio 66 sdo 64 dgnd 63 sync_o+ 62 sync_o? 61 dvdd33 60 dvdd18 59 nc 58 nc 57 p2d0 56 p2d1 55 p2d2 54 dgnd 53 dvdd18 52 p2d3 51 p2d4 65 pll_lock pin 1 100 avdd33 99 agnd 98 avdd33 97 agnd 96 avdd33 95 agnd 94 agnd 93 out1_p 92 out1_n 91 agnd 90 aux1_p 89 aux1_n 88 agnd 87 aux2_n 86 aux2_p 85 agnd 84 out2_n 83 out2_p 82 agnd 81 agnd 80 avdd33 79 agnd 78 avdd33 77 agnd 76 avdd33 26 p1d6 27 p1d5 28 p1d4 29 p1d3 30 p1d2 31 p1d1 32 dgnd 33 dvdd18 34 p1d0 35 nc 36 nc 37 dataclk 38 dvdd33 39 txenable/iqselect 40 p2d13 41 p2d12 42 p2d11 43 dvdd18 44 dgnd 45 p2d10 46 p2d9 47 p2d8 48 p2d7 49 p2d6 50 p2d5 2 cvdd18 3 cgnd 4 cgnd 7 cgnd 6 refclk? 5 refclk+ 1 cvdd18 8 cgnd 9 cvdd18 10 cvdd18 12 agnd 13 sync_i+ 14 sync_i? 15 dgnd 16 dvdd18 17 p1d13 18 p1d12 19 p1d11 20 p1d10 21 p1d9 22 dgnd 23 dvdd18 24 p1d8 25 p1d7 11 cgnd ad9778a top view (not to scale) analog domain digital domain nc = no connect 06452-003 notes 1. for optimal thermal performance, the exposed pad should be soldered to the ground plane for the 100-lead, thermally enhanced tqfp package. figure 4. ad9778a pin configuration table 8. ad9778a pin fu nction descriptions pin no. mnemonic description 1 cvdd18 1.8 v clock supply. 2 cvdd18 1.8 v clock supply. 3 cgnd clock ground. 4 cgnd clock common. 5 refclk+ differential clock input. 6 refclk? differential clock input. 7 cgnd clock ground. 8 cgnd clock ground. 9 cvdd18 1.8 v clock supply. 10 cvdd18 1.8 v clock supply. 11 cgnd clock ground. 12 agnd analog ground. 13 sync_i+ differential synchronization input. 14 sync_i? differential synchronization input. 15 dgnd digital ground. 16 dvdd18 1.8 v digital supply. 17 p1d13 port 1, data input d13 (msb). 18 p1d12 port 1, data input d12. pin no. mnemonic description 19 p1d11 port 1, data input d11. 20 p1d10 port 1, data input d10. 21 p1d9 port 1, data input d9. 22 dgnd digital ground. 23 dvdd18 1.8 v digital supply. 24 p1d8 port 1, data input d8. 25 p1d7 port 1, data input d7. 26 p1d6 port 1, data input d6. 27 p1d5 port 1, data input d5. 28 p1d4 port 1, data input d4. 29 p1d3 port 1, data input d3. 30 p1d2 port 1, data input d2. 31 p1d1 port 1, data input d1. 32 dgnd digital ground. 33 dvdd18 1.8 v digital supply. 34 p1d0 port 1, data input d0 (lsb). 35 nc no connect. 36 nc no connect.
ad9776a/ad9778a/AD9779A rev. b | page 13 of 56 pin no. mnemonic description 37 dataclk data clock output. 38 dvdd33 3.3 v digital supply. 39 txenable/ iqselect transmit enable. in single port mode, this pin also functions as iqselect. 40 p2d13 port 2, data input d13 (msb). 41 p2d12 port 2, data input d12. 42 p2d11 port 2, data input d11. 43 dvdd18 1.8 v digital supply. 44 dgnd digital ground. 45 p2d10 port 2, data input d10. 46 p2d9 port 2, data input d9. 47 p2d8 port 2, data input d8. 48 p2d7 port 2, data input d7. 49 p2d6 port 2, data input d6. 50 p2d5 port 2, data input d5. 51 p2d4 port 2, data input d4. 52 p2d3 port 2, data input d3. 53 dvdd18 1.8 v digital supply. 54 dgnd digital ground. 55 p2d2 port 2, data input d2. 56 p2d1 port 2, data input d1. 57 p2d0 port 2, data input d0 (lsb). 58 nc no connect. 59 nc no connect. 60 dvdd18 1.8 v digital supply. 61 dvdd33 3.3 v digital supply. 62 sync_o? differential synchronization output. 63 sync_o+ differential synchronization output. 64 dgnd digital ground. 65 pll_lock pll lock indicator. 66 sdo 3-wire interface port data output. 67 sdio 3-wire interface port data input/output. 68 sclk 3-wire interface port clock. 69 csb 3-wire interface port chip select bar. 70 reset reset, active high. pin no. mnemonic description 71 irq interrupt request. 72 agnd analog ground. 73 iptat factory test pin. output current is proportional to absolute temperature, approximately 14 a at 25c with approximately 20 na/c slope. this pin should remain floating. 74 vref voltage reference output. 75 i120 120 a reference current. 76 avdd33 3.3 v analog supply. 77 agnd analog ground. 78 avdd33 3.3 v analog supply. 79 agnd analog ground. 80 avdd33 3.3 v analog supply. 81 agnd analog ground. 82 agnd analog ground. 83 out2_p differential dac current output, channel 2. 84 out2_n differential dac current output, channel 2. 85 agnd analog ground. 86 aux2_p auxiliary dac current output, channel 2. 87 aux2_n auxiliary dac current output, channel 2. 88 agnd analog ground. 89 aux1_n auxiliary dac current output, channel 1. 90 aux1_p auxiliary dac current output, channel 1. 91 agnd analog ground. 92 out1_n differential dac current output, channel 1. 93 out1_p differential dac current output, channel 1. 94 agnd analog ground. 95 agnd analog ground. 96 avdd33 3.3 v analog supply. 97 agnd analog ground. 98 avdd33 3.3 v analog supply. 99 agnd analog ground. 100 avdd33 3.3 v analog supply.
ad9776a/ad9778a/AD9779A rev. b | page 14 of 56 74 vref 73 iptat 72 agnd 69 csb 70 reset 71 irq 75 i120 68 sclk 67 sdio 66 sdo 64 dgnd 63 sync_o+ 62 sync_o? 61 dvdd33 60 dvdd18 59 p2d0 58 p2d1 57 p2d2 56 p2d3 55 p2d4 54 dgnd 53 dvdd18 52 p2d5 51 p2d6 65 pll_lock pin 1 100 avdd33 99 agnd 98 avdd33 97 agnd 96 avdd33 95 agnd 94 agnd 93 out1_p 92 out1_n 91 agnd 90 aux1_p 89 aux1_n 88 agnd 87 aux2_n 86 aux2_p 85 agnd 84 out2_n 83 out2_p 82 agnd 81 agnd 80 avdd33 79 agnd 78 avdd33 77 agnd 76 avdd33 26 p1d8 27 p1d7 28 p1d6 29 p1d5 30 p1d4 31 p1d3 32 dgnd 33 dvdd18 34 p1d2 35 p1d1 36 p1d0 37 dataclk 38 dvdd33 39 txenable/iqselect 40 p2d15 41 p2d14 42 p2d13 43 dvdd18 44 dgnd 45 p2d12 46 p2d11 47 p2d10 48 p2d9 49 p2d8 50 p2d7 2 cvdd18 3 cgnd 4 cgnd 7 cgnd 6 refclk? 5 refclk+ 1 cvdd18 8 cgnd 9 cvdd18 10 cvdd18 12 agnd 13 sync_i+ 14 sync_i? 15 dgnd 16 dvdd18 17 p1d15 18 p1d14 19 p1d13 20 p1d12 21 p1d11 22 dgnd 23 dvdd18 24 p1d10 25 p1d9 11 cgnd AD9779A top view (not to scale) analog domain digital domain 06452-004 notes 1. for optimal thermal performance, the exposed pad should be soldered to the ground plane for the 100-lead, thermally enhanced tqfp package. figure 5. AD9779A pin configuration table 9. AD9779A pin fu nction descriptions pin no. mnemonic description pin no. mnemonic description 1 cvdd18 1.8 v clock supply. 19 p1d13 port 1, data input d13. 2 cvdd18 1.8 v clock supply. 3 cgnd clock ground. 4 cgnd clock ground. 5 refclk+ differential clock input. 6 refclk? differential clock input. 7 cgnd clock ground. 8 cgnd clock ground. 9 cvdd18 1.8 v clock supply. 10 cvdd18 1.8 v clock supply. 11 cgnd clock ground. 12 agnd analog ground. 13 sync_i+ differential synchronization input. 14 sync_i? differential synchronization input. 15 dgnd digital ground. 16 dvdd18 1.8 v digital supply. 17 p1d15 port 1, data input d15 (msb). 18 p1d14 port 1, data input d14. 20 p1d12 port 1, data input d12. 21 p1d11 port 1, data input d11. 22 dgnd digital ground. 23 dvdd18 1.8 v digital supply. 24 p1d10 port 1, data input d10. 25 p1d9 port 1, data input d9. 26 p1d8 port 1, data input d8. 27 p1d7 port 1, data input d7. 28 p1d6 port 1, data input d6. 29 p1d5 port 1, data input d5. 30 p1d4 port 1, data input d4. 31 p1d3 port 1, data input d3. 32 dgnd digital ground. 33 dvdd18 1.8 v digital supply. 34 p1d2 port 1, data input d2. 35 p1d1 port 1, data input d1. 36 p1d0 port 1, data input d0 (lsb).
ad9776a/ad9778a/AD9779A rev. b | page 15 of 56 pi n no. mnemonic description 37 dataclk data clock output. 38 dvdd33 3.3 v digital supply. 39 txenable/ iqselect transmit enable. in single port mode, this pin also functions as iqselect. 40 p2d15 port 2, data input d15 (msb). 41 p2d14 port 2, data input d14. 42 p2d13 port 2, data input d13. 43 dvdd18 1.8 v digital supply. 44 dgnd digital ground. 45 p2d12 port 2, data input d12. 46 p2d11 port 2, data input d11. 47 p2d10 port 2, data input d10. 48 p2d9 port 2, data input d9. 49 p2d8 port 2, data input d8. 50 p2d7 port 2, data input d7. 51 p2d6 port 2, data input d6. 52 p2d5 port 2, data input d5. 53 dvdd18 1.8 v digital supply. 54 dgnd digital ground. 55 p2d4 port 2, data input d4. 56 p2d3 port 2, data input d3. 57 p2d2 port 2, data input d2. 58 p2d1 port 2, data input d1. 59 p2d0 port 2, data input d0 (lsb). 60 dvdd18 1.8 v digital supply. 61 dvdd33 3.3 v digital supply. 62 sync_o? differential synchronization output. 63 sync_o+ differential synchronization output. 64 dgnd digital ground. 65 pll_lock pll lock indicator. 66 sdo 3-wire interface port data output. 67 sdio 3-wire interface port data input/output. 68 sclk 3-wire interface port clock. 69 csb 3-wire interface port chip select bar. 70 reset reset, active high. pin no. mnemonic description 71 irq interrupt request. 72 agnd analog ground. 73 iptat factory test pin. output current is proportional to absolute temperature, approximately 14 a at 25c with approximately 20 na/c slope. this pin should remain floating. 74 vref voltage reference output. 75 i120 120 a reference current. 76 avdd33 3.3 v analog supply. 77 agnd analog ground. 78 avdd33 3.3 v analog supply. 79 agnd analog ground. 80 avdd33 3.3 v analog supply. 81 agnd analog ground. 82 agnd analog ground. 83 out2_p differential dac current output, channel 2. 84 out2_n differential dac current output, channel 2. 85 agnd analog ground. 86 aux2_p auxiliary dac current output, channel 2. 87 aux2_n auxiliary dac current output, channel 2. 88 agnd analog ground. 89 aux1_n auxiliary dac current output, channel 1. 90 aux1_p auxiliary dac current output, channel 1. 91 agnd analog ground. 92 out1_n differential dac current output, channel 1. 93 out1_p differential dac current output, channel 1. 94 agnd analog ground. 95 agnd analog ground. 96 avdd33 3.3 v analog supply. 97 agnd analog ground. 98 avdd33 3.3 v analog supply. 99 agnd analog ground. 100 avdd33 3.3 v analog supply.
ad9776a/ad9778a/AD9779A rev. b | page 16 of 56 typical performance characteristics 4 ?6 0 code inl (16-bit lsb) 3 2 1 0 ?1 ?2 ?3 ?4 ?5 10k 20k 30k 60k 50k 40k 06452-005 figure 6. AD9779A typical inl 1.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 0 60k 50k 40k 30k 20k 10k code dnl (16-bit lsb) 0 6452-006 figure 7. AD9779A typical dnl 100 50 0 100 f out (mhz) sfdr (dbc) 90 80 70 60 20 40 60 80 f data = 160msps f data = 200msps f data = 250msps 06452-007 figure 8. AD9779A in-band sfdr vs. f out , 1 interpolation 100 50 0 100 f out (mhz) sfdr (dbc) 90 80 70 60 20 40 60 80 f data = 160msps f data = 200msps f data = 250msps 06452-008 figure 9. AD9779A in-band sfdr vs. f out , 2 interpolation 100 50 0 100 f out (mhz) sfdr (dbc) 90 80 70 60 20 40 60 80 f data = 100msps f data = 200msps f data = 150msps 06452-009 figure 10. AD9779A in-band sfdr vs. f out , 4 interpolation 100 50 0 50 f out (mhz) sfdr (dbc) 90 80 70 60 10 20 30 40 f data = 50msps f data = 100msps f data = 125msps 06452-010 figure 11. AD9779A in-band sfdr vs. f out , 8 interpolation
ad9776a/ad9778a/AD9779A rev. b | page 17 of 56 100 50 0 100 f out (mhz) sfdr (dbc) 90 80 70 60 20 40 60 80 f data = 200msps f data = 160msps f data = 250msps 06452-011 figure 12. AD9779A out-of-band sfdr vs. f out , 2 interpolation 100 50 0 100 f out (mhz) sfdr (dbc) 90 80 70 60 20 40 60 80 f data = 150msps f data = 100msps f data = 200msps 06452-012 figure 13. AD9779A out-of-band sfdr vs. f out , 4 interpolation 100 50 0 50 f out (mhz) sfdr (dbc) 90 80 70 60 10 20 30 40 f data = 50msps f data = 100msps f data = 125msps 06452-013 figure 14. AD9779A out-of-band sfdr vs. f out , 8 interpolation 100 50 0 40 f out (mhz) sfdr (dbc) 90 80 70 60 10 20 30 pll off pll on 06452-014 figure 15. AD9779A in-band sfdr vs. f out , 4 interpolation, f data = 100 msps, pll on/off 100 50 0 80 f out (mhz) sfdr (dbc) 90 80 70 60 20 40 60 ?3dbfs 0dbfs ?6dbfs 06452-015 figure 16. AD9779A in-band sfdr vs. f out , digital full scale 100 50 0 80 f out (mhz) sfdr (dbc) 90 80 70 60 20 40 60 10ma 20ma 30ma 06452-016 figure 17. AD9779A in-band sfdr vs. f out , output full-scale current
ad9776a/ad9778a/AD9779A rev. b | page 18 of 56 100 50 0 120 f out (mhz) imd (dbc) 90 80 70 60 20 40 60 80 100 f data = 200msps f data = 250msps f data = 160msps 06452-017 figure 18. AD9779A third-order imd vs. f out , 1 interpolation 100 50 0 20 40 60 80 100 120 140 160 180 200 220 f out (mhz) imd (dbc) 90 80 70 60 f data = 160msps f data = 250msps f data = 200msps 06452-018 figure 19. AD9779A third-order imd vs. f out , 2 interpolation 100 50 0 400 f out (mhz) imd (dbc) 90 80 70 60 40 80 120 160 200 240 280 320 360 f data = 150msps f data = 200msps f data = 100msps 06452-019 figure 20. AD9779A third-order imd vs. f out , 4 interpolation f out (mhz) imd (dbc) f data = 75msps f data = 125msps f data = 100msps 90 100 80 70 60 50 450 425 400 375 350 325 300 275 250 225 200 175 150 125 100 75 50 25 0 f data = 50msps 06452-020 figure 21. AD9779A third-order imd vs. f out , 8 interpolation 100 50 0 200 f out (mhz) imd (dbc) 90 80 70 60 100 20 40 60 80 120 140 160 180 pll off pll on 06452-021 figure 22. AD9779A third-order imd vs. f out , 4 interpolation, f data = 100 msps, pll on/off 100 95 50 55 0 400 360 f out (mhz) imd (dbc) 90 80 85 70 75 60 65 40 80 120 160 200 240 280 320 06452-022 figure 23. AD9779A third-order imd vs. f out , over 50 parts, 4 interpolation, f data = 200 msps
ad9776a/ad9778a/AD9779A rev. b | page 19 of 56 100 50 55 60 65 70 75 80 85 90 95 0 400 f out (mhz) imd (dbc) 80 160 240 360320 40 120 200 280 0dbfs ?3dbfs ?6dbfs 06452-117 figure 24. AD9779A imd performance vs. f out , digital full-scale input over output frequency, 4 interpolation, f data = 200 msps 100 50 55 60 65 70 75 80 85 90 95 0 400 f out (mhz) imd (dbc) 80 160 240 360320 40 120 200 280 20ma 10ma 30ma 06452-118 figure 25. AD9779A imd performance vs. f out , full-scale output current over output frequency, 4 interpolation, f data = 200 msps stop 400.0mhz sweep 1.203s (601 pts) vbw 20khz start 1.0mhz *res bw 20khz ref 0dbm *peak log 10db lgav 51 w1 s3 (f): ftun swp s2 fc aa *atten 20db ext ref dc-coupled 06452-023 figure 26. AD9779A single tone, 4 interpolation, f data = 100 msps, f out = 30 mhz stop 400.0mhz sweep 1.203s (601 pts) vbw 20khz start 1.0mhz *res bw 20khz ref 0dbm *peak log 10db lgav 51 w1 s3 (f): ftun swp s2 fc aa *atten 20db ext ref dc-coupled 06452-024 figure 27. AD9779A two-tone spectrum, 4 interpolation, f data = 100 msps, f out = 30 mhz, 35 mhz ?142 ?146 ?150 ?154 ?158 ?162 ?166 ?170 0 f out (mhz) nsd (dbm/hz) 20 40 60 80 0dbfs ?3dbfs ?6dbfs 06452-025 figure 28. AD9779A noise spectral density vs. f out , digital full-scale over output fr equency of single-tone input, 2 interpolation, f data = 200 msps ? 150 ?170 0 100 f out (mhz) nsd (dbm/hz) ?154 ?158 ?162 ?166 20 40 60 80 f dac = 800msps f dac = 400msps f dac = 200msps 06452-026 figure 29. AD9779A noise spectral density vs. f out , f dac over output frequency for eight-to ne input with 500 khz spacing, f data = 200 msps
ad9776a/ad9778a/AD9779A rev. b | page 20 of 56 ? 150 ?170 0 100 f out (mhz) nsd (dbm/hz) ?154 ?158 ?162 ?166 20 40 60 80 f dac = 800msps f dac = 400msps f dac = 200msps 06452-027 figure 30. AD9779A noise spectral density vs. f out , f dac over output frequency with a single-tone input at ?6 dbfs ? 55 ?90 ?85 ?80 ?75 ?70 ?65 ?60 0 260240220200180160 140 12010080 60 4020 f out (mhz) aclr (dbc) 06452-300 0dbfs, pll disabled ?3dbfs, pll disabled ?6dbfs, pll disabled 0dbfs, pll enabled figure 31. AD9779A aclr for first adjacent band w-cdma, 4 interpolation, f data = 122.88 msps, on-chip modulation translates baseband signal to if span 50mhz sweep 162.2ms (601 pts) vbw 300khz center 143.88mhz *res bw 30khz rms results carrier power ?12.49dbm/ 3.84000mhz freq offset 5.000mhz 10.00mhz 15.00mhz ref bw 3.840mhz 3.840mhz 3.840mhz dbc ?76.75 ?80.94 ?79.95 dbm ?89.23 ?93.43 ?92.44 lower dbc ?77.42 ?80.47 ?78.96 dbm ?89.91 ?92.96 ?91.45 upper ref ?25.28dbm *avg log 10db pavg 10 w1 s2 *atten 4db ext ref 0 6452-031 figure 32. AD9779A w-cdma signal, 4 interpolation, f data = 122.88 msps, f dac /4 modulation ? 55 ?90 ?85 ?80 ?75 ?70 ?65 ?60 0 260240 220 20018016014012010080604020 f out (mhz) aclr (dbc) 06452-301 ?3dbfs, pll disabled ?6dbfs, pll disabled 0dbfs, pll enabled 0dbfs, pll disabled figure 33. AD9779A aclr for second adjacent band w-cdma, 4 interpolation, f data = 122.88 msps, on-chip modulation translates baseband signal to if ? 55 ?90 ?85 ?80 ?75 ?70 ?65 ?60 0 260240 220 20018016014012010080604020 f out (mhz) aclr (dbc) 06452-302 ?3dbfs, pll disabled ?6dbfs, pll disabled 0dbfs, pll enabled 0dbfs, pll disabled figure 34. AD9779A aclr for third adjacent band w-cdma, 4 interpolation, f data = 122.88 msps, on-chip modulation translates baseband signal to if span 50mhz sweep 162.2ms (601 pts) vbw 300khz center 151.38mhz *res bw 30khz 1 ?17.87dbm 2 ?20.65dbm 3 ?18.26dbm 4 ?18.23dbm total carrier power ?12.61dbm/15.3600mhz ref carrier power ?17.87dbm/3.84000mhz freq offset 5.000mhz 10.00mhz 15.00mhz integ bw 3.840mhz 3.840mhz 3.840mhz dbc ?67.70 ?70.00 ?71.65 dbm ?85.57 ?97.87 ?99.52 lower dbc ?67.70 ?69.32 ?71.00 dbm ?85.57 ?87.19 ?88.88 upper ref ?30.28dbm *avg log 10db pavg 10 w1 s2 *atten 4db ext ref 06452-032 figure 35. AD9779A multicarrier w-cdma signal, 4 interpolation, f dac = 122.88 msps, f dac /4 modulation
ad9776a/ad9778a/AD9779A rev. b | page 21 of 56 1.5 0 code inl (14-bit lsb) 10k 1.0 0.5 0 ?0.5 ?1.0 ?1.5 2k 4k 6k 8k 0 6452-033 figure 36. ad9778a typical inl 0.6 0 code dnl (14-bit lsb) ?0.2 ?1.0 16k 14k 12k 10k 8k 6k 4k 2k 0.4 0.2 0 ?0.4 ?0.6 ?0.8 06452-034 figure 37. ad9778a typical dnl 100 50 0 400 f out (mhz) imd (dbc) 90 80 70 60 40 80 120 160 200 240 280 320 360 4 200msps 4 150msps 4 100msps 06452-035 figure 38. ad9778a imd vs. f out , 4 interpolation 100 50 0 100 f out (mhz) sfdr (dbc) 90 80 70 60 20 40 60 80 f data = 250msps f data = 200msps f data = 160msps 06452-036 figure 39. ad9778a in-band sfdr vs. f out , 2 interpolation ?90 0 250 f out (mhz) aclr (dbc) ?70 ?80 ?60 25 50 75 100 125 150 175 200 225 first adjacent channel second adjacent channel third adjacent channel 06452-037 figure 40. ad9778a aclr, single carrier w-cdma, 4 interpolation, f data = 122.88 msps, amplitude = ?3 dbfs span 50mhz sweep 162.2ms (601 pts) vbw 300khz center 143.88mhz *res bw 30khz rms results carrier power ?12.74dbm/ 3.84000mhz freq offset 5.000mhz 10.00mhz 15.00mhz ref bw 3.884mhz 3.840mhz 3.840mhz dbc ?76.49 ?80.13 ?80.90 dbm ?89.23 ?92.87 ?93.64 lower dbc ?76.89 ?80.02 ?79.53 dbm ?89.63 ?92.76 ?92.27 upper ref ?25.39dbm *avg log 10db pavg 10 w1 s2 *atten 4db 0 6452-038 figure 41. ad9778a aclr, f data = 122.88 msps, 4 interpolation, f dac /4 modulation
ad9776a/ad9778a/AD9779A rev. b | page 22 of 56 ? 150 ?170 0 100 f out (mhz) nsd (dbm/hz) ?154 ?158 ?162 ?166 20 40 60 80 f dac = 800msps f dac = 400msps f dac = 200msps 06452-039 figure 42. ad9778a noise spectral density vs. f out for eight-tone input with 500 khz spacing, f data = 200 msps ? 150 ?170 0 100 f out (mhz) nsd (dbm/hz) ?154 ?158 ?162 ?166 20 40 60 80 f dac = 800msps f dac = 400msps f dac = 200msps 06452-040 figure 43. ad9778a noise spectral density vs. f out with single-tone input at ?6 dbfs, f data = 200 msps 0.4 0 4096 code inl (12-bit lsb) ?0.4 512 1024 2560 2048 1536 3072 3584 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 06452-041 figure 44. ad9776a typical inl 0.20 0 4096 code dnl (12-bit lsb) 2048 ?0.20 512 1024 1536 2560 3072 3584 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 06452-042 figure 45. ad9776a typical dnl 100 50 0 400 f out (mhz) imd (dbc) 40 80 120 160 200 240 280 320 360 4 200msps 4 100msps 4 150msps 95 90 85 80 75 70 65 60 55 06452-043 figure 46. ad9776a imd vs. f out , 4 interpolation 100 50 0 100 f out (mhz) sfdr (dbc) 90 80 70 60 20 40 60 80 f data = 250msps f data = 200msps f data = 160msps 06452-044 figure 47. ad9776a in-band sfdr vs. f out , 2 interpolation
ad9776a/ad9778a/AD9779A rev. b | page 23 of 56 ?90 0 250 f out (mhz) aclr (dbc) ? 55 25 50 75 100 125 150 175 200 225 ?60 ?65 ?70 ?75 ?80 ?85 06452-045 first adjacent channel second adjacent channel third adjacent channel figure 48. ad9776a aclr vs. f out , f data = 122.88 msps, 4 interpolation, f dac /4 modulation span 50mhz sweep 162.2ms (601 pts) vbw 300khz center 143.88mhz *res bw 30khz rms results carrier power ?12.67dbm/ 3.84000mhz freq offset 5.000mhz 10.00mhz 15.00mhz ref bw 3.884mhz 3.840mhz 3.840mhz dbc ?75.00 ?78.05 ?77.73 dbm ?87.67 ?90.73 ?90.41 lower dbc ?75.30 ?77.99 ?77.50 dbm ?87.97 ?90.66 ?90.17 upper ref ?25.29dbm *avg log 10db pavg 10 w1 s2 *atten 4db 0 6452-046 figure 49. ad9776a single carrier w-cdma, 4 interpolation, f data = 122.88 msps, amplitude = ?3 dbfs ? 150 ?170 0 100 f out (mhz) nsd (dbm/hz) ?154 ?158 ?162 ?166 20 40 60 80 f dac = 800msps f dac = 400msps f dac = 200msps 10 30 50 70 90 06452-047 figure 50. ad9776a noise spectral density vs. f out , eight-tone input with 500 khz spacing, f data = 200 msps ? 150 ?170 0 100 f out (mhz) nsd (dbm/hz) ?154 ?158 ?162 ?166 20 40 60 80 f dac = 800msps f dac = 400msps f dac = 200msps 10 30 50 70 90 06452-048 figure 51. ad9776a noise spectral density vs. f out , single-tone input at ?6 dbfs, f data = 200 msps
ad9776a/ad9778a/AD9779A rev. b | page 24 of 56 terminology integral nonlinearity (inl) inl is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. differential nonlinearity (dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a dac is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current at code 0 from the ideal of zero is called offset error. for i outa , 0 ma output is expected when the inputs are all 0s. for i outb , 0 ma output is expected when all inputs are set to 1s. gain error gain error is the difference between the actual and the ideal output spans. the actual span is determined by the difference between the full-scale output and the bottom-scale output. output compliance range output compliance range is the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. temp er atu re d r i f t temperature drift is specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full- scale range (fsr) per degree celsius. for reference drift, the drift is reported in ppm per degree celsius. power supply rejection (psr) psr is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. settling time settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. in-band spurious-free dynamic range (sfdr) in-band sfdr is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate. out-of-band spurious-free dynamic range (sfdr) out-of-band sfdr is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the band that starts at the frequency of the input data rate and ends at the nyquist frequency of the dac output sample rate. normally, energy in this band is rejected by the interpolation filters. this specification, therefore, defines how well the inter- polation filters work and the effect of other parasitic coupling paths to the dac output. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured fundamental. it is expressed as a percentage or in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. interpolation filter if the digital inputs to the dac are sampled at a multiple rate of f data (interpolation rate), a digital filter can be constructed that has a sharp transition band near f data /2. images that typically appear around f dac (output data rate) can be greatly suppressed. adjacent channel leakage ratio (aclr) aclr is the ratio in dbc of the measured power within a channel relative to its adjacent channel. complex image rejection in a traditional two-part upconversion, two images are created around the second if frequency. these images have the effect of wasting transmitter power and system bandwidth. by placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second if can be rejected.
ad9776a/ad9778a/AD9779A rev. b | page 25 of 56 theory of operation the ad9776a/ad9778a/AD9779A have many features that make them highly suited for wired and wireless communications systems. the dual digital signal path and dual dac structure allow an easy interface with common quadrature modulators when designing single sideband transmitters. the speed and performance of the parts allow wider bandwidths and more carriers to be synthesized than in previously available dacs. the digital engine uses an innovative filter architecture that combines the interpolation with a digital quadrature modulator. this allows the parts to perform digital quadrature frequency upconversions. the on-chip synchronization circuitry enables multiple devices to be synchronized to each other, or to a system clock. differences between ad9776/ad9778/ ad9779 and ad9776a/ad9778a/AD9779A refclk maximum fre quency vs. supply with some restrictions on the dvdd18 and cvdd18 power supplies, the ad9776a/ad9778a/AD9779A support a maxi- mum sample rate of 1100 mhz. table 2 lists the valid operating frequencies vs. power supply voltage. refclk amplitude with a differential sinusoidal clock applied to refclk, the pll on the ad9776/ad9778/ad9779 does not achieve optimal noise performance unless the refclk differential amplitude is increased to 2 v p-p. note that if an lvpecl driver is used on the ad9776/ad9778/ad9779, the pll exhibits optimal performance if the refclk amplitude is well within lvpecl specifications (<1.6 v p-p differential). the design of the pll on the AD9779A has been improved so that even with a sinusoidal clock, the pll still achieves optimal amplitude if the swing is 1.6 v p-p. pll lock ranges the individual lock ranges for the ad9776a/ad9778a/AD9779A pll are wider than those for the ad9776/ad9778/ad9779. this means that the ad9776a/ad9778a/AD9779A pll remains in lock in a given range over a wider temperature range than the ad9776/ad9778/ad9779. see table 2 3 for pll lock ranges for the ad9776a/ad9778a/AD9779A. pll optimal settings the optimal settings for the ad9776/ad9778/ad9779 differ from the ad9776a/ad9778a/AD9779A. refer to the pll bias settings section for complete details. input data delay line, manual and automatic correction modes the ad9776a/ad9778a/AD9779A can be programmed to not only sense when the timing margin on the input data falls below a preset threshold but to also take action. the device can be programmed to either set the irq (pin and register) or automatically reoptimize the timing input data timing. input data timing see table 28 for timing specifications vs. temperature. the input data timing specifications (setup and hold) are different for the ad9776a/ad9778a/AD9779A than they are for the ad9776/ad9778/ad9779. dataclk delay range in the ad9776/ad9778/ad9779, the input data delay was controlled by register 0x04, bits[7:4]. at 25c, the delay was stepped by approximately 180 ps/increment. in the ad9776a/ ad9778a/AD9779A, an extra bit has been added, which effectively doubles the delay range. this bit is now located at register 0x01, bit 1. the increment/step on the ad9776a/ad9778a/AD9779A remains at ~180 ps. version register the version register (register 0x1f) of the ad9776a/ad9778a/ AD9779A reads a value of 0x07. the version register of the ad9776/ad9778/ad9779 reads a value of 0x03. table 10. register value differences betw een ad9776/ad9778/ad9779 and ad9776a/ad9778a/AD9779A part no. pll loop bandwidth, register 0x0a, bits[4:0] pll bias, register 0x09, bits[2:0] vco control voltage, register 0x0a, bits[7:5] pll vco drive, register 0x08, bits[1:0] ad9776/ad9778/ad9779 11111 111 010 00 ad9776a/ad9778a/AD9779A 01111 011 011 11
ad9776a/ad9778a/AD9779A rev. b | page 26 of 56 3-wire interface the 3-wire port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard micro- controllers and microprocessors. the port is compatible with most synchronous transfer formats, including both the motorola spi and intel? ssr protocols. the interface allows read and write access to all registers that configure the ad9776a/ad9778a/AD9779A. single- or multiple-byte transfers are supported, as well as msb-first or lsb-first transfer formats. serial data input/output can be accomplished through a single bidirectional pin (sdio) or through two unidirectional pins (sdio/sdo). the serial port configuration is controlled by register 0x00, bits[7:6]. it is important to note that any change made to the serial port configuration occurs immediately upon writing to the last bit of this byte. therefore, it is possible with a multibyte transfer to write to this register and change the configuration in the middle of a communication cycle. care must be taken to compensate for the new configuration within the remaining bytes of the current communication cycle. use of a single-byte transfer when changing the serial port configuration is recommended to prevent unexpected device behavior. as described in this section, all serial port data is transferred to/from the device in synchronization with the sclk pin. if synchronization is lost, the device has the ability to asynchro- nously terminate an i/o operation, putting the serial port controller into a known state and, thereby, regaining synchro- nization. sdo spi port 66 sdio 67 s clk 68 csb 69 0 6452-049 figure 52. 3-wire interface port general operation of the serial interface there are two phases of a communication cycle with the ad9776a/ad9778a/AD9779A. phase 1 is the instruction cycle (the writing of an instruction byte into the device), coinciding with the first eight sclk rising edges. the instruction byte provides the serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is a read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the device. a logic high on the csb pin followed by a logic low resets the 3-wire interface port timing to the initial state of the instruction cycle. from this state, the next eight rising sclk edges represent the instruction bits of the current i/o operation, regardless of the state of the internal registers or the other signal levels at the inputs to the 3-wire interface port. if the 3-wire interface port is in an instruction cycle or a data transfer cycle, none of the present data is written. the remaining sclk edges are for phase 2 of the communica- tion cycle. phase 2 is the actual data transfer between the device and the system controller. phase 2 of the communication cycle is a transfer of one, two, three, or four data bytes, as determined by the instruction byte. using one multibyte transfer is preferred. single-byte data transfers are useful in reducing cpu overhead when register access requires only one byte. registers change immediately upon writing to the last bit of each transfer byte. instruction byte see table 11 for information contained in the instruction byte. table 11. 3-wire interface instruction byte msb lsb i7 i6 i5 i4 i3 i2 i1 i0 r/ w n1 n0 a4 a3 a2 a1 a0 r/ w , bit 7 of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. logic 1 indicates a read operation. logic 0 indicates a write operation. n1 and n0, bit 6 and bit 5 of the instruction byte, determine the number of bytes to be transferred during the data transfer cycle. the translation for the number of bytes to be transferred is listed in table 12 . a4, a3, a2, a1, and a0bit 4, bit 3, bit 2, bit 1, and bit 0, respectively, of the instruction bytedetermine the register that is accessed during the data transfer portion of the communication cycle. for multibyte transfers, this address is the starting byte address. the remaining register addresses are generated by the device, based on the lsb-first bit (register 0x00, bit 6). table 12. byte transfer count n1 n0 description 0 0 transfer one byte 0 1 transfer two bytes 1 0 transfer three bytes 1 1 transfer four bytes
ad9776a/ad9778a/AD9779A rev. b | page 27 of 56 serial interface port pin descriptions serial clock (sclk) the serial clock pin synchronizes data to and from the device and controls the internal state machines. the maximum frequency of sclk is 40 mhz. all data input is registered on the rising edge of sclk. all data is driven out on the falling edge of sclk. chip select (csb) active low input starts and gates a communication cycle. it allows more than one device to be used on the same serial communication lines. the sdo and sdio pins go to a high impedance state when this input is high. chip select should stay low during the entire communication cycle. serial data i/o (sdio) data is always written into the device on this pin. however, this pin can be used as a bidirectional data line. the configuration of this pin is controlled by register 0x00, bit 7. the default is logic 0, configuring the sdio pin as unidirectional. serial data out (sdo) data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the device operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state. msb/lsb transfers the serial port can support both msb-first and lsb-first data formats. this functionality is controlled by the lsb-/msb-first register bit (register 0x00, bit 6). the default is msb-first format (lsb/msb first = 0). when msb-first format is selected (lsb/msb first = 0), the instruction and data bit must be written from msb to lsb. multibyte data transfers in msb-first format start with an instruction byte that includes the register address of the most significant data byte. subsequent data bytes should follow from high address to low address. in msb-first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle. when lsb/msb first = 1 (lsb first) the instruction and data bit must be written from lsb to msb. multibyte data transfers in lsb-first format start with an instruction byte that includes the register address of the least significant data byte, followed by multiple data bytes. the serial port internal byte address genera- tor increments for each byte of the multibyte communication cycle. the serial port controller data address decrements from the data address written toward 0x00 for multibyte i/o operations if the msb-first format is active. the serial port controller address increments from the data address written toward 0x1f for multibyte i/o operations if the lsb-first format is active. r/w n1 n0 a4 a3 a2 a1 a0 d7 d6 n d5 n d0 0 d1 0 d2 0 d3 0 d7 d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle data transfer cycle csb sclk sdio sdo 06452-050 figure 53. serial register interface timing, msb first a0 a1 a2 a3 a4 n0 n1 r/w d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n instruction cycle data transfer cycle csb sclk sdio sdo 06452-051 figure 54. serial register interface timing, lsb first instruction bit 6 instruction bit 7 csb sclk sdio t ds t ds t dh t pwh t pwl t sclk 06452-052 figure 55. timing diagram for 3-wire interface register write data bit n ? 1 data bit n csb sclk sdio sdo t dv 0 6452-053 figure 56. timing diagram for 3-wire interface register read
ad9776a/ad9778a/AD9779A rev. b | page 28 of 56 3-wire interface register map note that all unused register bits should be kept at the device default values. table 13. register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def. hex decimal comm 0x00 00 sdio bidirectional lsb/msb first software reset power- down mode auto power- down enable pll lock indicator (read only) 0x00 digital control 0x01 01 interpolation factor[1:0] fi lter modulation mode[3:0] dataclk delay[4] zero stuffing enable 0x00 0x02 02 data format single port real mode dataclk delay enable inverse sinc enable dataclk invert txenable invert q first 0x00 sync control 0x03 03 dataclk delay mode reserved (set to 1) dataclk divide[1:0] data timing margin[3:0] 0x00 0x04 04 dataclk delay[3:0] sync_o divide[2:0] sync_o delay[4] 0x00 0x05 05 sync_o delay[3:0] sync_i ratio[2:0] sync_i delay[4] 0x00 0x06 06 sync_i delay[3:0] sy nc_i timing margin[3:0] 0x00 0x07 07 sync_i enable sync_o enable sync_o triggering edge clock state[4:0] 0x00 pll control 0x08 08 pll band select[5:0] pll vco drive[1:0] 0xe7 0x09 09 pll enable pll vco divi de ratio[1:0] pll loop divide ratio[1:0] pll bias[2:0] 0x52 misc. control 0x0a 10 vco control voltage[2:0] (rea d only) pll loop bandwidth[4:0] 0x1f i dac control 0x0b 11 i dac gain adjustment[7:0] 0xf9 0x0c 12 i dac sleep i dac power- down i dac gain adjustment[9:8] 0x01 aux dac1 control 0x0d 13 auxiliary dac1 data[7:0] 0x00 0x0e 14 auxiliary dac1 sign auxiliary dac1 current direction auxiliary dac1 power- down auxiliary dac1 data[9:8] 0x00 q dac control 0x0f 15 q dac gain adjustment[7:0] 0xf9 0x10 16 q dac sleep q dac power- down q dac gain adjustment[9:8] 0x01 aux dac2 control 0x11 17 auxiliary dac2 data[7:0] 0x00 0x12 18 auxiliary dac2 sign auxiliary dac2 current direction auxiliary dac2 power- down auxiliary dac2 data[9:8] 0x00 0x13 to 0x18 19 to 24 reserved interrupt 0x19 25 data timing error irq sync timing error irq data timing error type data timing error irq enable sync timing error irq enable internal sync loopback 0x00 version 0x1f 31 version[7:0] 0x07
ad9776a/ad9778a/AD9779A rev. b | page 29 of 56 table 14. 3-wire interface register description register address bits register name parameter function default comm 0x00 7 sdio bidirectional 0: use sdio pin as input data only. 1: use sdio as both input and output data. 0 0x00 6 lsb/msb first 0: first bit of serial data is msb of data byte. 1: first bit of serial data is lsb of data byte. 0 0x00 5 software reset bit must be written with a 1 and then 0 to soft reset the 3-wire interface register map. 0 0x00 4 power-down mode 0: all circuitry is active. 1: disable all digital and analog circuitry, only 3-wire interface port is active. 0x00 3 auto power-down enable controls auto power-down mode. see the power- down and sleep modes section. 0 0x00 1 pll lock indicator (read only) 0: pll is not locked. 1: pll is locked. digital control 0x01 7:6 interpolation factor[1:0] 00: 1 interpolation. 01: 2 interpolation. 10: 4 interpolation. 11: 8 interpolation. 00 0x01 5:2 filter modulation mode[3:0] see table 19 for filter modes. 0000 0x01 1 dataclk delay[4] sets msb of delay of refclk input to dataclk output. 0 0x01 0 zero stuffing enable 0: zero stuffing off. 1: zero stuffing on. 0 0x02 7 data format 0: twos compliment. 1: unsigned binary. 0 0x02 6 single port 0: both p1d and p2d data ports enabled. 1: data for both dacs received on p1d data port. 0 0x02 5 real mode 0: enable q path for signal processing. 1: disable q path data (internal q channel clocks disabled, i and q modulators disabled). 0 0x02 4 dataclk delay enable enables the dataclk delay feature. more details on this feature are shown in the optimizing the data input timing section. 0x02 3 inverse sinc enable 0: inverse sinc filter disabled. 1: inverse sinc filter enabled. 0 0x02 2 dataclk invert 0: output dataclk same ph ase as internal data sampling clock, dclk_smp signal. 1: output dataclk opposite phase as internal data sampling clock, dclk_smp signal. 0 0x02 1 txenable invert inverts the polarity of pin 39, the txenable input pin (also functions as iqselect). 0 0x02 0 q first 0: in interleaved mode, the i data precedes the q data on the input port. 1: in interleaved mode, the q data precedes the i data on the input port.
ad9776a/ad9778a/AD9779A rev. b | page 30 of 56 register address bits register name parameter function default sync control 0x03 7 dataclk delay mode 0: manual data timing error detect mode. 1: automatic data timing error detect mode. 0 0x03 6 reserved should always be set to 1. 0 0x03 5:4 dataclk divide[1:0] dataclk output divider value. 00: divide by 1. 01: divide by 2. 10: divide by 4. 11: divide by 1. 00 0x03 3:0 data timing margin[3:0] sets the timing margin required to prevent the data timing error irq bit from being asserted. 0000 0x04 7:4 dataclk delay[3:0] sets delay of refclk input to dataclk output (see table 29 for details). 0000 0x04 3:1 sync_o divide[2:0] the frequency of the sync_o signal is equal to f dac /n, where n is set as follows: 000: n = 32. 001: n = 16. 010: n = 8. 011: n = 4. 100: n = 2. 101: n = 1. 110: n = undefined. 111: n = undefined. 000 0x04 0x05 0 7:4 sync_o delay[4] sync_o delay[3:0] the sync_o delay[4:0] value programs the value of the delay line of the sync_o signal. the delay of sync_o is relative to refclk. the delay line resolution is 80 ps per step. 00000: nominal delay. 00001: adds 80 ps delay to sync_o. 00010: adds 160 ps delay to sync_o. 11111: adds 2480 ps delay to sync_o. 0 0000 0x05 3:1 sync_i ratio[2:0] this value controls the number of sync_i input pulses required to generate a synchronization pulse (see table 30 for details). 000 0x05 0x06 0 7:4 sync_i delay[4] sync_i delay[3:0] the sync_i delay[4:0] value programs the value of the delay line of the sync_i signal. the delay line resolution is 80 ps per step. 00000: nominal delay. 00001: adds 80 ps delay to sync_i. 00010: adds 160 ps delay to sync_i. 11111: adds 2480 ps delay to sync_i. 0 0000 0x06 3:0 sync_i timing margin[3:0] 0000 0x07 7 sync_i enable 1: enables the sync_i input. 0 0x07 6 sync_o enable 1: enables the sync_o output. 0 0x07 5 sync_o triggering edge 0: sync_o changes on refclk falling edge. 1: sync_o changes on refclk rising edge. 0 0x07 4:0 clock state[4:0] this value determines the state of the internal clock generation state machine upon synchronization. 0
ad9776a/ad9778a/AD9779A rev. b | page 31 of 56 register address bits register name parameter function default pll control 0x08 7:2 pll band select[5:0] this sets the operating frequency range of the vco. for details (see table 23 ). 111001 0x08 1:0 pll vco drive[1:0] controls the signal streng th of the vco output. set to 11 for optimal performance. 11 0x09 7 pll enable 0: pll off, dac sample clock is sourced directly by the refclk input. 1: pll on, dac clock synthesized internally from refclk input via pll clock multiplier. 0 0x09 6:5 pll vco divide ratio[1:0] sets the value of the vco output divider, which determines the ratio of the vco output frequency to the dac sample clock frequency, f vco /f dacclk . 00: f vco /f dacclk = 1. 01: f vco /f dacclk = 2. 10: f vco /f dacclk = 4. 11: f vco /f dacclk = 8. 10 0x09 4:3 pll loop divide ratio[1:0] sets the value of the dacclk divider, which determines the ratio of the dac sample clock frequency to the refclk frequency, f dacclk /f refclk . 00: f dacclk /f refclk = 2. 01: f dacclk /f refclk = 4. 10: f dacclk /f refclk = 8. 11: f dacclk /f refclk = 16. 10 0x09 2:0 pll bias[2:0] controls vco bias current. set to 011 for optimal performance. 010 misc. control 0x0a 7:5 vco control voltage[2:0] (read only) 000 to 111, proportional to voltage at vco control voltage input, readback only. a value of 011 indicates the vco centered in its frequency range. 000 0x0a 4:0 pll loop bandwidth[4:0] controls the bandwidth of the pll filter. increasing the value lowers the loop bandwidth. set to 01111 for optimal performance. 11111 i dac control 0x0c 0x0b 1:0 7:0 i dac gain adjustment[9:8] i dac gain adjustment[7:0] the i dac gain adjustment[9:0] value is the i dac 10-bit gain setting word. bit 9 is the msb and bit 0 is the lsb. 01 11111001 0x0c 7 i dac sleep 0: i dac on. 1: i dac off, but reference remains powered. 0 0x0c 6 i dac power-down 0: i dac on. 1: i dac off. 0 aux dac1 control 0x0e 0x0d 1:0 7:0 auxiliary dac1 data[9:8] auxiliary dac1 data[7:0] the auxiliary dac 1 data [9:0] value is the aux dac1 10-bit output current control word. magnitude of the auxiliary dac current increases with increasing value. bit 9 is the msb and bit 0 is the lsb. 00 00000000 0x0e 7 auxiliary dac1 sign 0: aux1_p active. 1: aux1_n active. 0 0x0e 6 auxiliary dac1 current direction 0: source. 1: sink. 0 0x0e 5 auxiliary dac1 power-down 0: auxiliary dac1 on. 1: auxiliary dac1 off. 0 q dac control 0x10 0x0f 1:0 7:0 q dac gain adjustment[9:8] q dac gain adjustment[7:0] the q dac gain adjustment[9:0] value is the q dac 10-bit gain setting word. bit 9 is the msb and bit 0 is the lsb. 01 11111001 0x10 7 q dac sleep 0: q dac on. 1: q dac off. 0 0x10 6 q dac power-down 0: q dac on. 1: q dac off. 0
ad9776a/ad9778a/AD9779A rev. b | page 32 of 56 register address bits register name parameter function default aux dac2 control 0x12 0x11 1:0 7:0 auxiliary dac2 data[9:8] auxiliary dac2 data[7:0] auxiliary dac2 data[9:0] is the 10-bit output current control word. magnitude of the auxiliary dac current increases with increasing value. bit 9 is the msb and bit 0 is the lsb. 00 00000000 0x12 7 auxiliary dac2 sign 0: aux2_p active. 1: aux2_n active. 0 0x12 6 auxiliary dac2 current direction 0: source. 1: sink. 0 0x12 5 auxiliary dac2 power-down 0: auxiliary dac2 on. 1: auxiliary dac2 off. 0 0x13 to 0x18 reserved interrupt 0x19 7 data timing error irq read only. active high indicates a timing violation occurred on the input data port. the irq is latched. this bit is cleared when the interrupt register is read. 0 0x19 6 sync timing error irq read only. active high indicates a timing violation occurred on the sync_i input. the irq is latched. this bit is cleared when the interrupt register is read. 0 0x19 4 data timing error type read only. indicates the timing error type. 0: hold time violation. 1: setup time violation. meaningful when data timing error irq is active. 0 0x19 3 data timing error irq enable 0: data timing error irq is masked. 1: data timing error irq is enabled. 0 0x19 2 sync timing error irq enable 0: sync timing error irq is masked. 1: sync timing error irq is enabled. 0 0x19 0 internal sync loopback the received sync_o signal is looped back to the sync_i signal. 0 version 0x1f 7:0 version[7:0] indicates device hardware revision number. 00000111
ad9776a/ad9778a/AD9779A rev. b | page 33 of 56 interpolation filter architecture the ad9776a/ad9778a/AD9779A can provide up to 8 inter- polation, or the interpolation filters can be entirely disabled. it is important to note that the input signal should be backed off by approximately 0.01 db from full scale to avoid overflowing the interpolation filters. the coefficients of the low-pass filters and the inverse sinc filter are given in tabl e 15 , table 16 , table 1 7 , and table 18 . spectral plots for the filter responses are shown in figure 57 , figure 58 , and figure 59 . table 15. low-pass filter 1 lower coefficient upper coefficient integer value h(1) h(55) ?4 h(2) h(54) 0 h(3) h(53) +13 h(4) h(52) 0 h(5) h(51) ?34 h(6) h(50) 0 h(7) h(49) +72 h(8) h(48) 0 h(9) h(47) ?138 h(10) h(46) 0 h(11) h(45) +245 h(12) h(44) 0 h(13) h(43) ?408 h(14) h(42) 0 h(15) h(41) +650 h(16) h(40) 0 h(17) h(39) ?1003 h(18) h(38) 0 h(19) h(37) +1521 h(20) h(36) 0 h(21) h(35) ?2315 h(22) h(34) 0 h(23) h(33) +3671 h(24) h(32) 0 h(25) h(31) ?6642 h(26) h(30) 0 h(27) h(29) +20,755 h(28) +32,768 table 16. low-pass filter 2 lower coefficient upper coefficient integer value h(1) h(23) ?2 h(2) h(22) 0 h(3) h(21) +17 h(4) h(20) 0 h(5) h(19) ?75 h(6) h(18) 0 h(7) h(17) +238 h(8) h(16) 0 h(9) h(15) ?660 h(10) h(14) 0 h(11) h(13) +2530 h(12) +4096 table 17. low-pass filter 3 lower coefficient upper coefficient integer value h(1) h(15) ?39 h(2) h(14) 0 h(3) h(13) +273 h(4) h(12) 0 h(5) h(11) ?1102 h(6) h(10) 0 h(7) h(9) +4964 h(8) +8192 table 18. inverse sinc filter lower coefficient upper coefficient integer value h(1) h(9) +2 h(2) h(8) ?4 h(3) h(7) +10 h(4) h(6) ?35 h(5) +401 10 ?100 ?4 4 f out ( input data rate) attenuation (db) ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 06452-054 figure 57. 2 interpolation, low-pass response to 4 input data rate (dotted lines indica te 1 db roll-off)
ad9776a/ad9778a/AD9779A rev. b | page 34 of 56 10 ?100 ?4 4 f out ( input data rate) attenuation (db) ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 06452-055 figure 58. 4 interpolation, low-pass response to 4 input data rate (dotted lines indica te 1 db roll-off) 10 ?100 ?4 4 f out ( input data rate) attenuation (db) ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 06452-056 figure 59. 8 interpolation, low-pass response to 4 input data rate (dotted lines indica te 1 db roll-off) with the interpolation filter and modulator combined, the incoming signal can be placed anywhere within the nyquist region of the dac output sample rate. when the input signal is complex, this architecture allows modulation of the input signal to positive or negative nyquist regions (see table 19 ). the nyquist regions of up to 4 the input data rate can be seen in figure 60 . ?4 ? 8 ?3 ? 6 ?2 ? 4 ?1 ? 2 dc 1 1 3 2 5 3 7 ? 7 ? 5 ? 3 ? 1246 4 08 06452-086 figure 60. nyquist zones figure 57 , figure 58 , and figure 59 show the low-pass response of the digital filters with no modulation. by turning on the modu- lation feature, the response of the digital filters can be tuned to anywhere within the dac bandwidth. as an example, figure 61 to figure 67 show the nonshifted mode filter responses for 8 interpolation (refer to table 19 for shifted/nonshifted mode filter responses). 10 ?100 ?4 4 ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 f out ( input data rate) attenuation (db) 06452-058 figure 61. interpolation/modulation combination of 4f dac /8 filter 10 ?100 ?4 4 ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 f out ( input data rate) attenuation (db) 06452-059 figure 62. interpolation/modulation combination of ?3f dac /8 filter 10 ?100 ?4 4 ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 f out ( input data rate) attenuation (db) 06452-060 figure 63. interpolation/modulation combination of ?2f dac /8 filter
ad9776a/ad9778a/AD9779A rev. b | page 35 of 56 10 ?100 ?4 4 ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 f out ( input data rate) attenuation (db) 06452-061 10 ?100 ?4 4 ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 f out ( input data rate) attenuation (db) 06452-064 figure 64. interpolation/modulation combination of ?f dac /8 filter figure 67. interpolation/modulation combination of 3f dac /8 filter shifted mode filter responses allow the pass band to be centered around 0.5 f data , 1.5 f data , 2.5 f data , and 3.5 f data . switching to the shifted mode response does not affect the center frequency of the signal. instead, the pass band of the filter is simply shifted. for example, use the response shown in figure 67 and assume the signal in-band is a complex signal over the bandwidth 3.2 f data to 3.3 f data . if the shifted mode filter response is then selected, the pass band becomes centered at 3.5 f data . however, the signal remains at the same place in the spectrum. the shifted mode capability allows the filter pass band to be placed anywhere in the dac nyquist bandwidth. 10 ?100 ?4 4 ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 f out ( input data rate) attenuation (db) 06452-062 the ad9776a/ad9778a/AD9779A are dual dacs with internal complex modulators built into the interpolating filter response. in dual channel mode, the devices expect the real and imaginary components of a complex signal at digital input port 1 and digital input port 2 (i and q, respectively). the dac outputs then represent the real and imaginary components of the input signal, modulated by the complex carrier (f dac /2, f dac /4, or f dac /8). figure 65. interpolation/modulation combination of f dac /8 filter 10 ?100 ?4 4 ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 f out ( input data rate) attenuation (db) 06452-063 with register 0x02, bit 6, set, the device accepts interleaved data on port 1 in the i, q, i, q sequence. note that in interleaved mode, the channel data rate at the beginning of the i and q data paths is now half the input data rate because of the interleaving. the maximum input data rate is still subject to the maximum specification of the device. this limits the synthesis bandwidth available at the input in interleaved mode. with register 0x02, bit 5 (the real mode bit), set, the q channel and the internal i and q digital modulation are turned off. the output spectrum at the i dac then represents the signal at digital input port 1, interpolated by 1, 2, 4, or 8. the general recommendation is that if the desired signal is within 0.4 f data , use the nonshifted filter mode. outside of this, the shifted filter mode should be used. in any situation, the total bandwidth of the signal is less than 0.8 f data . figure 66. interpolation/modulation combination of 2f dac /8 filter
ad9776a/ad9778a/AD9779A rev. b | page 36 of 56 table 19. interpolation filter modes, (register 0x01, bits[5:2]) interpolation factor[7:6] filter modulation mode[5:2] modulation nyquist zone pass band frequency normalized to f dac comments low center high 8 0x00 dc 0 ?0.05 0 +0.05 in 8 interpolation; bw (min) = 0.0375 f dac bw (max) = 0.1 f dac 8 0x01 dc shifted +1 +0.0125 +0.0625 +0.1125 8 0x02 f dac /8 +2 +0.075 +0.125 +0.175 8 0x03 f dac /8 shifted +3 +0.1375 +0.1875 +0.2375 8 0x04 f dac /4 +4 +0.2 +0.25 +0.3 8 0x05 f dac /4 shifted +5 +0.2625 +0.3125 +0.3625 8 0x06 3f dac /8 +6 +0.325 +0.375 +0.425 8 0x07 3f dac /8 shifted +7 +0.3875 +0.4375 +0.4875 8 0x08 f dac /2 8 ?0.55 ?0.5 ?0.45 8 0x09 f dac /2 shifted ?7 ?0.4875 ?0.4375 ?0.3875 8 0x0a ?3f dac /8 ?6 ?0.425 ?0.375 ?0.343 8 0x0b ?3f dac /8 shifted ?5 ?0.3625 ?0.3125 ?0.2625 8 0x0c ?f dac /4 ?4 ?0.3 ?0.25 ?0.2 8 0x0d ?f dac /4 shifted ?3 ?0.2375 ?0.1875 ?0.1375 8 0x0e ?f dac /8 ?2 ?0.175 ?0.125 ?0.075 8 0x0f ?f dac /8 shifted ?1 ?0.1125 ?0.0625 ?0.0125 4 0x00 dc 0 ?0.1 0 +0.1 in 4 interpolation; bw (min) = 0.075 f dac bw (max) = 0.2 f dac 4 0x01 dc shifted +1 +0.025 +0.125 +0.225 4 0x02 f dac /4 +2 +0.15 +0.25 +0.35 4 0x03 f dac /4 shifted +3 +0.275 +0.375 +0.475 4 0x04 f dac /2 4 ?0.6 ?0.5 ?0.4 4 0x05 f dac /2 shifted ?3 ?0.475 ?0.375 ?0.275 4 0x06 ?f dac /4 ?2 ?0.35 ?0.25 ?0.15 4 0x07 ?f dac /4 shifted ?1 ?0.225 ?0.125 ?0.025 2 0x00 dc 0 ?0.2 0 +0.2 in 2 interpolation; bw (min) = 0.15 f dac bw (max) = 0.4 f dac 2 0x01 dc shifted +1 +0.05 +0.25 +0.45 2 0x02 f dac /2 2 ?0.7 ?0.5 ?0.3 2 0x03 f dac /2 shifted ?1 ?0.45 ?0.25 ?0.05
ad9776a/ad9778a/AD9779A rev. b | page 37 of 56 interpolation filter bandwidth limits the ad9776a/ad9778a/AD9779A use a novel interpolation filter architecture that allows dac if frequencies to be gener- ated anywhere in the spectrum. figure 68 shows the traditional choice of dac if output bandwidth placement. note that there are no possible filter modes in which the carrier can be placed near 0.5 f data , 1.5 f data , 2.5 f data , and so on. 10 ?80 ?4 4 f out ( input data rate), assuming 8 interpolation attenuation (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?3?2?10123 + f dac /2 + f dac /4 + f dac /8 baseband ? f dac /8 ? f dac /4 ? f dac /2 06452-065 figure 68. traditional bandwidt h options for txdac output if the filter architecture not only allows the interpolation filter pass bands to be centered in the middle of the input nyquist zones (as explained in this section), but also allows the possi- bility of a 3 f dac /8 modulation mode when interpolating by 8. with all of these filter combinations, a carrier of given bandwidth can be placed anywhere in the spectrum and fall into a possible pass band of the interpolation filters. the possible bandwidths accessible with the filter architecture are shown in figure 69 and figure 70 . note that the shifted and nonshifted filter modes are all accessible by programming the filter mode for a particular interpolation rate. 10 ?80 ?4 4 f out ( input data rate), assuming 8 interpolation attenuation (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?3 ?2 ?1 0 1 2 3 ? f dac /2 ?3 f dac /8 ? f dac /4 ? f dac /8 baseband + f dac /8 + f dac /4 +3 f dac /8 + f dac /2 06452-066 figure 69. nonshifted bandwidths acce ssible with the filter architecture 10 ?80 ?4 4 f out ( input data rate), assuming 8 interpolation attenuation (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?3?2?10123 shifted ? 3 f dac /8 shifted ? f dac /4 shifted ? f dac /8 shifted ? dc shifted + dc shifted + f dac /8 shifted + f dac /4 shifted + 3 f dac /8 06452-087 figure 70. shifted bandwidths accessible with the filter architecture with this filter architecture, a signal placed anywhere in the spectrum is possible. however, the signal bandwidth is limited by the input sample rate of the dac and the specific placement of the carrier in the spectrum. the bandwidth restriction resulting from the combination of filter response and input sample rate is often referred to as the synthesis bandwidth, because this is the largest bandwidth that the dac can synthesize. the maximum bandwidth condition exists if the carrier is placed directly in the center of one of the filter pass bands. in this case, the total 0.1 db bandwidth of the interpolation filters is equal to 0.8 f data . as table 19 shows, the synthesis band- width as a fraction of the dac output sample rate drops by a factor of 2 for every doubling of interpolation rate. the mini- mum bandwidth condition exists, for example, if a carrier is placed at 0.25 f data . in this situation, if the nonshifted filter response is enabled, the high end of the filter response cuts off at 0.4 f data , thus limiting the high end of the signal bandwidth. if the shifted filter response is instead enabled, then the low end of the filter response cuts off at 0.1 f data , thus limiting the low end of the signal bandwidth. the minimum bandwidth speci- fication that applies for a carrier at 0.25 f data is therefore 0.3 f data . the minimum bandwidth behavior is repeated over the spectrum for carriers placed at (n 0.25) f data , where n is any integer. digital modulation the digital quadrature modulation occurs within the interpolation filter. the modulation shifts the frequency spectrum of the incoming data by the frequency offset selected. the frequency offsets available are multiples of the input data rate. the modulation is equivalent to multiplying the quadrature input signal by a complex carrier signal, c(t), of the following form: c ( t ) = cos( c t ) + j sin( c t )
ad9776a/ad9778a/AD9779A rev. b | page 38 of 56 table 21. inverse sinc filter as shown in table 20 , the mixing functions of most of the modes result in cross-coupling of samples between the i and q channels. the i and q channels only operate independently with the f s /2 mode. this means that real modulation using both the i and q dac outputs can only be done in the f s /2 mode. all other modulation modes require complex input data and produce complex output signals. lower coefficient upper coefficient integer value h(1) h(9) +2 h(2) h(8) ?4 h(3) h(7) +10 h(4) h(6) ?35 h(5) n/a +401 table 20. modulation mixing sequences modulation the inverse sinc filter is disabled by default. it can be enabled by setting the inverse sinc enable bit (bit 3) in register 0x02. mixing sequence f dac /2 i = i, ?i, i, ?i, 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 ?3.5 ?4.0 ?4.5 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 f/f sample (db) 06452-088 sinc ?1 response combined sinc and sinc ?1 response q = q, ?q, q, ?q, f dac /4 i = i, q, ?i, ?q, q = q, ?i, ?q, i, ?f dac /4 i = i, ?q, ?i, q, q = q, i, ?q, ?i, f dac /8 i = i, r(i + q), q, r(?i + q), ?i, ?r(i + q), ?q, r(i ? q), q = q, r(q ? i), ?i, ?r(q + i), ?q, r(?q + i), i, r(q + i), where r = 2/2 inverse sinc filter the inverse sinc filter is implemented as a nine-tap fir filter. it is designed to provide less than 0.05 db pass-band ripple up to a frequency of 0.4 f data . to provide the necessary gain at the upper end of the pass band, the inverse sinc filter has an intrinsic insertion loss of 3.4 db. the transfer function is shown in figure 71 and the tap coefficients are given in table 21 . figure 71. transfer function of inverse si nc filter with the dac sin(x)/x output
ad9776a/ad9778a/AD9779A rev. b | page 39 of 56 sourcing the dac sample clock the ad9776a/ad9778a/AD9779A offer two modes of sourcing the dac sample clock (dacclk). the first mode employs an on-chip clock multiplier that accepts a reference clock operating at the lower input frequency, most commonly the data input frequency. the on-chip pll then multiplies the reference clock up to a higher frequency, which can then be used to generate all of the internal clocks required by the dac. the clock multiplier provides a high quality clock that meets the performance require- ments of most applications. using the on-chip clock multiplier removes the burden of generating and distributing the high speed dacclk at the board level. the second mode bypasses the clock multiplier circuitry and allows dacclk to be directly sourced through the refclk pins. this mode enables the user to source a very high quality input clock directly to the dac core. sourcing the dacclk directly through the refclk pins may be necessary in demanding applications that require the lowest possible dac output noise at higher output frequencies. in either case (that is, using the on-chip clock multiplier or sourcing the dacclk directly though the refclk pins), it is necessary that the refclk signal have low jitter to maximize the dac noise performance. direct clocking when the pll is disabled (register 0x09, bit 7 = 0), the refclk input is used directly as the dac sample clock (dacclk). the frequency of refclk needs to be the input data rate multiplied by the interpolation factor (and by an additional factor of 2 if zero stuffing is enabled). clock multiplication when the pll is enabled (register 0x09, bit 7 = 1), the clock multiplication circuit generates the dac sample clock from the lower rate refclk input. the functional diagram of the clock multiplier is shown in figure 72 . adc phase detector vco loop filter pin 65 and 0x00[1] pll lock detect refclk (pin 5, pin 6) 0x0a[7:5] pll control voltage 0x09[7] pll enable dacclk dataclk out (pin 37) 0x01[7:6] interpolation factor 0x09[6:5] pll vco divisor 0x09[4:3] pll loop divisor if n 2 n 1 0x08[7:2] vco band select 06452-092 figure 72. clock multiplier circuit the clock multiplier circuit operates such that the vco outputs a frequency, f vco , equal to the refclk input signal frequency multiplied by n1 n2. )( n2n1 ff refclk vco = the dac sample clock frequency, f dacclk , is equal to n2 ff refclk dacclk = when the pll is enabled, the maximum input clock frequency f refclk is 250 mhz. the values of n1 and n2 must be chosen to keep f vco in the optimal operating range of 1.0 ghz to 2.0 ghz. once the vco output frequency is known, the correct pll band select (register 0x08, bits[7:2]) value can be chosen. pll bias settings there are three bias settings for the pll circuitry that should be programmed to their nominal values. the pll values shown in table 22 are the recommended settings for these parameters. table 22. pll settings pll 3-wire interface control address optimal setting register bits pll loop bandwidth 0x0a [4:0] 01111 pll vco drive 0x08 [1:0] 11 pll bias 0x09 [2:0] 011 the pll loop bandwidth variable configures the bandwidth of the pll loop filter. a setting of 00000 configures the bandwidth to be approximately 1 mhz. a setting of 11111 configures the bandwidth to be approximately 10 mhz. the optimal value of 01111 sets the loop bandwidth to be approximately 3 mhz. configuring the pll band select value the pll vco has a valid operating range from approximately 1.0 ghz to 2.0 ghz. this range is covered in 63 overlapping frequency bands, as shown in table 23 . for any desired vco output frequency, there are multiple valid pll band select values. it is important to note that the data shown in table 23 is for a typical device. device-to-device variations can shift the actual vco output frequency range by 30 mhz to 40 mhz. in addition, the vco output frequency varies as a function of temperature. therefore, it is required that the optimal pll band select value be determined for each individual device at a particular operating temperature. the device has an automatic pll band select feature on chip. when this feature is enabled, the device determines the optimal pll band setting for the device at the given temperature. this setting holds for a 60c temperature swing in ambient tem- perature. if the device is operated in an environment that experiences a larger temperature swing, an offset should be applied to the automatically selected pll band.
ad9776a/ad9778a/AD9779A rev. b | page 40 of 56 table 23. typical vco frequency range vs. pll band select value pll lock ranges over temperature, ?40c to +85c pll band select vco frequency range (mhz) f low f high 111111 (63) auto mode 111110 (62) 1975 2026 111101 (61) 1956 2008 111100 (60) 1938 1992 111011 (59) 1923 1977 111010 (58) 1902 1961 111001 (57) 1883 1942 111000 (56) 1870 1931 110111 (55) 1848 1915 110110 (54) 1830 1897 110101 (53) 1822 1885 110100 (52) 1794 1869 110011 (51) 1779 1853 110010 (50) 1774 1840 110001 (49) 1748 1825 110000 (48) 1729 1810 101111 (47) 1730 1794 101110 (46) 1699 1780 101101 (45) 1685 1766 101100 (44) 1684 1748 101011 (43) 1651 1729 101010 (42) 1640 1702 101001 (41) 1604 1681 101000 (40) 1596 1658 100111 (39) 1564 1639 100110 (38) 1555 1606 100101 (37) 1521 1600 100100 (36) 1514 1575 100011 (35) 1480 1553 100010 (34) 1475 1529 100001 (33) 1439 1505 100000 (32) 1435 1489 pll lock ranges over temperature, ?40c to +85c pll band select vco frequency range (mhz) f low f high 011111 (31) 1402 1468 011110 (30) 1397 1451 011101 (29) 1361 1427 011100 (28) 1356 1412 011011 (27) 1324 1389 011010 (26) 1317 1375 011001 (25) 1287 1352 011000 (24) 1282 1336 010111 (23) 1250 1313 010110 (22) 1245 1299 010101 (21) 1215 1277 010100 (20) 1210 1264 010011 (19) 1182 1242 010010 (18) 1174 1231 010001 (17) 1149 1210 010000 (16) 1141 1198 001111 (15) 1115 1178 001110 (14) 1109 1166 001101 (13) 1086 1145 001100 (12) 1078 1135 001011 (11) 1055 1106 001010 (10) 1047 1103 001001 (9) 1026 1067 001000 (8) 1019 1072 000111 (7) 998 1049 000110 (6) 991 1041 000101 (5) 976 1026 000100 (4) 963 1011 000011 (3) 950 996 000010 (2) 935 981 000001 (1) 922 966 000000 (0) 911 951
ad9776a/ad9778a/AD9779A rev. b | page 41 of 56 configuring pll band select with temperature sensing the following procedure outlines a method for setting the pll band select value for a device operating at a particular temperature that holds for a change in ambient temperature over the total ?40c to +85c operating range of the device without further user intervention. note that refclk must be applied to the device during this procedure. 1. program the values of n1 (register 0x09, bits[6:5]) and n2 (register 0x09, bits[4:3]), along with the pll settings shown in table 22 . 2. set the pll band (register 0x08, bits[7:2]) to 63 to enable pll auto mode. 3. wait for the pll_lock pin or the pll lock indicator (register 0x00, bit 1) to go high. this should occur within 5 ms. 4. read back the 6-bit pll band (register 0x08, bits[7:2]). 5. based on the temperature when the pll auto band select is performed, set the pll band indicated in either tabl e 24 or table 25 by rewriting the readback values into the pll band select parameter (register 0x08, bits[7:2]). this procedure requires temperature sensing upon start-up or reset of the device to optimally choose the pll band select value that holds over the entire operating temperature range. if the optimal band is in the range of 0 to 31 (lower vco frequency), refer to tabl e 24 . table 24. setting optimal pll band, when band is in the lower range (0 to 31) if system startup temperature is set pll band as follows ?40c to ?10c set pll band = readback band + 2 ?10c to +15c set pll band = readback band + 1 15c to 55c set pll band = readback band 55c to 85c set pll band = readback band ? 1 if the optimal band is in the range of 32 to 62 (higher vco frequency), refer to tabl e 25 . table 25. setting optimal pll band, when band is in the higher range (32 to 62) if system startup temperature is set pll band as follows ?40c to ?30c set pll band = readback band + 3 ?30c to ?10c set pll band = readback band + 2 ?10c to +15c set pll band = readback band + 1 15c to 55c set pll band = readback band 55c to 85c set pll band = readback band ? 1 kn own temperature calibration with memory if temperature sensing is not available in the system, a factory calibration at a known temperature is another method for guaranteeing lock over temperature. factory calibration can be performed as follows: 1. program the values of n1 (register 0x09, bits[6:5]) and n2 (register 0x09, bits[4:3]), along with the pll settings shown in table 22 . 2. set the pll band (register 0x08, bits[7:2]) to 63 to enable pll auto mode. 3. wait for the pll_lock pin or the pll lock indicator (register 0x00, bit 1) to go high. this should occur within 5 ms. 4. read back the 6-bit pll band (register 0x08, bits[7:2]). 5. based on the temperature when the pll auto band select is performed, store into nonvolatile memory the pll band indicated in either tabl e 24 or table 25 . on system power- up or restart, load the stored pll band value into the pll band select parameter (register 0x08, bits[7:2]). set-and-forget device option if the pll band select configuration methods described in the previous sections cannot be implemented in a particular system, there may be a screened device option that can satisfy the system requirements. this allows the user to preload a specific pll band select value for all devices that holds over temperature. example refclk and vco frequencies are shown in table 26 . table 26. typical vco frequency range vs. pll band select value f refclk (mh) f vco (mh) guaranteed pll band total pll divide ratio 59.73335 955.7336 2 16 61.44 1966.08 61 32 67.2 1075.2 11 16 76.8 1228.8 20 16 80.01 1280 23 16 81.92 1310.72 25 16 92.16 1474.56 34 16 112.0 1792.0 50 16 119.4667 955.7336 2 8 122.88 1966.08 61 16
ad9776a/ad9778a/AD9779A rev. b | page 42 of 56 driving the refclk input the refclk input requires a low jitter differential drive signal. the signal level can range from 400 mv p-p differential to 1.6 v p-p differential centered about a 400 mv input common- mode voltage. looking at the single-ended inputs, refclk+ or refclk?, each input pin can safely swing from 200 mv p-p to 800 mv p-p about the 400 mv common-mode voltage. although these input levels are not directly lvds compatible, refclk can be driven by an offset ac-coupled lvds signal, as shown in figure 73 . lvds_p_in refclk+ 50? 50? 0.1 f 0.1f lvds_n_in refclk? v cm = 400mv 06452-068 figure 73. lvds refclk drive circuit if a clean sine clock is available, it can be transformer-coupled to refclk, as shown in figure 73 . use of a cmos or ttl clock is also acceptable for lower sample rates. it can be routed through a cmos to lvds translator, and then ac-coupled as described in this section. alternatively, it can be transformer- coupled and clamped, as shown in figure 74 . 50? 50? t tl or cmos clk input refclk+ refclk? v cm = 400mv bav99zxct high speed dual diode 0.1 f 06452-069 figure 74. ttl or cmos refclk drive circuit a simple bias network for generating v cm is shown in figure 75 . it is important to use cvdd18 and cgnd for the clock bias circuit. any noise or other signal that is coupled onto the clock is multiplied by the dac digital input signal and can degrade dac performance. 0.1f 1nf 1nf v cm = 400mv cvdd18 cgnd 1k ? 287? 06452-070 figure 75. refclk v cm generator circuit
ad9776a/ad9778a/AD9779A rev. b | page 43 of 56 full-scale current generation i dac dac full-scale reference current current scaling i dac gain q dac gain q dac ad9776a/ad9778a/AD9779A vref 10k ? 1.2v band gap 0.1f i120 06452-073 internal reference full-scale current on the i dac and q dac can be set from 8.66 ma to 31.66 ma. initially, the 1.2 v band gap reference is used to set up a current in an external resistor connected to i120 (pin 75). a simplified block diagram of the reference circuitry is shown in figure 76 . the recommended value for the external resistor is 10 k, which sets up an i reference in the resistor of 120 a, which in turn provides a dac output full-scale current of 20 ma. because the gain error is a linear function of this resistor, a high precision resistor improves gain matching to the internal matching specification of the devices. gain drift over temperature is also affected by this resistor. a resistor with a low temperature coefficient is recommended in applications requiring good gain stability. figure 76. reference circuitry 35 0 0 1000 dac gain code i fs (ma) 30 25 20 15 10 5 200 400 600 800 06452-074 internal current mirrors provide a current-gain scaling, where the i dac or q dac gain is a 10-bit word in the 3-wire interface port register (register 0x0b, register 0x0c, register 0x0f, and register 0x10). the default value for the dac gain registers gives an i fs of approximately 20 ma. i fs is equal to 32 1024 6 12 27v 1.2 u uu dac gain r i fs figure 77. i fs vs. dac gain code
ad9776a/ad9778a/AD9779A rev. b | page 44 of 56 gain and offset correction analog quadrature modulators make it very easy to realize single sideband radios. however, there are several nonideal aspects of quadrature modulator performance. among these analog degradations are ? gain mismatch: the gain in the real and imaginary signal paths of the quadrature modulator may not be matched perfectly. this leads to less than optimal image rejection because the cancellation of the negative frequency image is less than perfect. ? local oscillator (lo) feedthrough: the quadrature mod- ulator has a finite dc-referred offset, as well as coupling from its lo port to the signal inputs. these can lead to significant spectral spurs at the frequency of the quadrature modulator lo. the ad9776a/ad9778a/AD9779A have the capability to correct for both of these analog degradations. note that these degradations drift over temperature; therefore, if close to optimal single sideband performance is desired, a scheme for sensing these degradations over temperature and correcting for them may be necessary. i/q channel gain matching gain matching is achieved by adjusting the values in the dac gain registers. for the i dac, these values are in the 0x0b and 0x0c i dac control registers. for the q dac, these values are in the 0x0f and 0x10 q dac control registers. these are 10-bit values. to perform gain compensation, raise or lower the value of one of these registers by a fixed step size and measure the amplitude of the unwanted image. if the unwanted image is increasing in amplitude, stop the procedure and try the same adjustment on the other dac control register. do this until the image rejection cannot be improved through further adjustment of these registers. it should be noted that lo feedthrough compensation is inde- pendent of gain. however, gain compensation can affect the lo compensation because the gain compensation may change the common-mode level of the signal. the dc offset of some modulators is common-mode level dependent. therefore, it is recommended that the gain adjustment be performed prior to lo compensation. auxiliary dac operation two auxiliary dacs are provided on the ad9776a/ad9778a/ AD9779A. the full-scale output current on these dacs is derived from the 1.2 v band gap reference and external resistor between the i120 pin and ground. the gain scale from the reference amplifier current (i reference ) to the auxiliary dac reference current is 16.67 ma with the auxiliary dac gain set to full scale (10-bit values, 3-wire interface register 0x0d and 3-wire interface register 0x11). this results in a full-scale current of approximately 2 ma for auxiliary dac1 and auxiliary dac2. the auxiliary dac structure is shown in figure 78 . only one of the two output pins of the auxiliary dac is active at a time. the inactive side goes to a high impedance state (>100 k). the active output pin is chosen by writing to bit 7 of register 0x0e and register 0x12. the active output can act as either a current source or a current sink. when sourcing current, the output compliance voltage is 0 v to 1.6 v. when sinking current, the output compliance voltage is 0.8 v to 1.6 v. the output pin is chosen to be a current source or current sink by writing to bit 6 of register 0x0e and register 0x12. 0 6452-303 auxp auxn p/n source/ sinc 0ma to 2m a (source) v bias 0ma to 2m a (sink) figure 78. auxiliary dac source/sink for ad9776a/ad9778a/ad97779a the magnitude of the auxiliary dac1 current is controlled by the 0x0d and 0x0e auxiliary dac1 control registers; the magnitude of the auxiliary dac2 current is controlled by the 0x11 and 0x12 auxiliary dac2 control registers. these auxiliary dacs have the ability to source or sink current. this is programmable via bit 6 in either auxiliary dac control register. the choice of sinking or sourcing should be made at circuit design time. there is no advantage to switching between current source or current sink once the circuit is in place. the auxiliary dacs can be used for lo cancellation when the dac output is followed by a quadrature modulator. this lo feedthrough is caused by the input-referred dc offset voltage of the quadrature modulator (and the dac output offset voltage mismatch) and may degrade system performance. typical dac-to-quadrature modulator interfaces are shown in figure 79 . often, the input common-mode voltage for the modulator is much higher than the output compliance range of the dac, making ac coupling or a dc level shift necessary. if the required common-mode input voltage on the quadrature modu- lator matches that of the dac, then the dc shown in figure 79 can be used. a low-pass or band-pass passive filter is recommended when spurious signals from the dac (distortion and dac images) at the quadrature modulator inputs may affect the system perfor- mance. placing the filter at the location shown in figure 79 allows easy design of the filter because the source and load impedances can easily be designed close to 50 .
ad9776a/ad9778a/AD9779A rev. b | page 45 of 56 rbip 50? rbin 50? 93 90 92 21 22 ibbn ibbp AD9779A rbqn 50? rbqp 50? 84 87 89 83 86 9 10 rsli 100? rslq 100? out1_n aux1_n aux2_n out1_p aux1_p out2_p aux2_p out2_n qbbp qbbn lpi 390nh lni 390nh 82pf c1i 39pf c2i lnq 390nh lpq 390nh 82pf c3q 39pf c2q 250 ? 500 ? 500 ? 500 ? 500 ? 250 ? 250 ? 250 ? 82pf c3i 82pf c1q 06452-093 figure 79. typical use of auxiliary dacs ac coupling to quadrature modulator lo feedthrough compensation the lo feedthrough compensation is the most complex of all three operations. this is due to the structure of the offset aux- iliary dacs, as shown in figure 78 . to achieve lo feedthrough compensation in a circuit, each of four outputs of these auxiliary dacs can be connected through a 500 resistor to ground and through a 250 resistor to one of the four quadrature modulator signal inputs. the purpose of these connections is to drive a very small amount of current into the nodes at the quadrature modulator inputs, therefore adding a slight dc bias to one of the quadrature modulator signal inputs. to achieve lo feedthrough compensation, the user should start with the default conditions of the auxiliary dac sign registers, and then increment the magnitude of one or the other auxiliary dac output currents. while this is being done, the amplitude of the lo feedthrough at the quadrature modulator output should be sensed. if the lo feedthrough amplitude increases, try either changing the sign of the auxiliary dac being adjusted or adjusting the output current of the other auxiliary dac. it may take practice before an effective algorithm is achieved. using the ad9776a/ad9778a/AD9779A evaluation board, the lo feedthrough can typically be adjusted down to the noise floor, although this is not stable over temperature. results of gain and offset correction the results of gain and offset correction can be seen in figure 80 and figure 81 . figure 80 shows the output spectrum of the quad- rature demodulator before gain and offset correction. figure 81 shows the output spectrum after correction. the lo feedthrough spur at 2.1 ghz has been suppressed to the noise level. this result can be achieved by applying the correction, but the correc- tion needs to be repeated after a large change in temperature. note that the gain matching improved the negative frequency image rejection, but there is still a significant image present. the remaining image is now due to phase mismatch in the quadrature modulator. phase mismatch can be distinguished from gain mismatch by the shape of the image. note that the image in figure 80 is relatively flat and the image in figure 81 slopes down with frequency. phase mismatch is frequency dependent, so an image dominated by phase mismatch has this sloping characteristic. 06452-304 span 200mhz center 2.1ghz ref lvl 0dbm 20mhz 0 ? 100 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 rbw 3khz ref att 30db vbw 3khz mixer ?40dbm swt 56s unit dbm figure 80. AD9779A and adl5372 with a multitone signal at 2.1 ghz, no gain or lo compensation 06452-305 span 200mhz center 2.1ghz ref lvl 0dbm 20mhz 0 ? 100 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 rbw 20khz ref att 20d b vbw 20khz mixer ?40dbm swt 1.25s unit dbm figure 81. AD9779A and adl5372 with a multitone signal at 2.1 ghz, gain and lo compensation optimized
ad9776a/ad9778a/AD9779A rev. b | page 46 of 56 input data ports dual port mode the ad9776a/ad9778a/AD9779A can operate in two data input modes: dual port mode and single port mode. for the default dual port mode (single port bit = 0), each dac receives data from a dedicated input port. in single port mode (single port bit = 1), both dacs receive data from port 1. in single port mode, dac1 and dac2 data is interleaved, and the txenable input is used to steer data to the intended dac. in dual port mode, the txenable input is used to power down the digital data path. in dual port mode, data for each dac is received on the respective input bus (p1d[15:0] or p2d[15:0]). i and q data arrive simultaneously and are sampled on the rising edge of the dataclk signal. the txenable signal must be high to enable the transmit path. input data referenced to dataclk the simplest method of interfacing to the ad9776a/ad9778a/ AD9779A is when the input data is referenced to the dataclk output. the dataclk output is a buffered version (with some fixed delay) of the internal clock that is used to latch the input data. therefore, if setup and hold times of the input data with respect to dataclk are met, the input data is latched correctly. detailed timing diagrams for the single and dual port cases using dataclk as the timing reference are shown in figure 82 . in dual port mode, the data must be delivered at the input data rate. in single port mode, data must be delivered at twice the input data rate of each dac. because the data inputs function up to a maximum of 300 msps, it is practical to operate with input data rates up to 150 mhz per dac in single port mode. in dual port and single port modes, a data clock output (dataclk) signal is available as a fixed time base with which to drive data from an fpga or other data source. this output signal operates at the input data rate. dataclk data t sdataclk t hdataclk 06452-308 single port mode in single port mode, data for both dacs is received on the port 1 input bus (p1d[15:0]). i and q data samples are interleaved and are sampled on the rising edges of dataclk. along with the data, a framing signal must be supplied on the txenable input (pin 39), which steers incoming data to its respective dac. when txenable is high, the corresponding data-word is sent to the i dac. when txenable is low, the corresponding data is sent to the q dac. the timing of the digital interface in interleaved mode is shown in figure 83 . figure 82. input data port timing, data referenced to dataclk table 28 shows the setup and hold time requirements for the input data over the operating temperature range of the device. also shown is the keep out window (kow). the keep out window is the sum of the setup and hold times of the interface. this is the minimum amount of time valid data must be presented to the device to ensure proper sampling. dataclk frequency settings the dataclk signal is derived from the internal dac sample clock, dacclk. the frequency of the dataclk output depends on several programmable settings. normally, the frequency of dataclk is equal to the input data rate. the relationship between the frequency of dacclk and dataclk is the q first bit (register 0x02, bit 0) controls the pairing order of the input data. with the q first bit set to the default of 0, the i-q pairing sent to the dacs is the two input data-words corresponding to txenable low followed by txenable high. with the q first bit set to 1, the i-q pairing sent to the dacs is the two input data-words corresponding to txenable high, followed by txenable low. note that with either order pairing, the data sent with txenable high is directed to the i dac, and the data sent with txenable low is directed to the q dac. dataclkdiv spzsif f f dacclk dataclk = where the variables if , zs, sp , and dataclkdiv have the values shown in table 27 . 06452-306 dataclk p1d[15:0] txenable i dac[15:0] q dac[15:0] i dac[15:0] q dac[15:0] q first = 1 q first = 0 p1d1 p1d2 p1d3 p1d4 p1d5 p1d6 p1d7 p1d8 p1d1 p1d3 p1d5 p1d1 p1d0 p1d3 p1d5 p1d2 p1d4 p1d6 p1d2 p1d4 figure 83. single port mode digital interface timing
ad9776a/ad9778a/AD9779A rev. b | page 47 of 56 the dataclkdiv only affects the dataclk output frequency, not the frequency of the data sampling clock. to maintain an f dataclk frequency that samples the input data that remains consistent with the expected data rate, dataclkdiv should be set to 00. table 27. dacclk to dataclk divisor values variable value address register bit if interpolation factor (1, 2, 4, or 8) 0x01 [7:6] zs 1, if zero stuffing is disabled 2, if zero stuffing is enabled 0x01 [0] sp 0.5, if single port is enabled 1, if dual port is selected 0x02 [6] dataclkdiv 1, 2, or 4 0x03 [5:4] input data referenced to refclk in some systems, it may be more convenient to use the refclk input than the dataclk output as the input data timing reference. if the frequency of dacclk is equal to the frequency of the data input (without interpolation), then the data with respect to refclk timing specifications in table 28 apply directly without further considerations. if the frequency of dacclk is greater than the frequency of the input data, a divider is used to generate the dataclk output (and the internal data sampling clock). this divider creates a phase ambiguity between refclk and dataclk, which results in uncertainty in the sampling time. to establish fixed setup and hold times of the data interface, this phase ambiguity must be eliminated. to eliminate the phase ambiguity, the sync_i input pins (pin 13 and pin 14) must be used to force the data to be sampled on a specific refclk edge. the relationship among refclk, sync_i, and input data is shown in figure 84 and figure 85 . therefore, both sync_i and data must meet the timing in table 28 for reliable data transfer into the device. 06452-309 t srefclk t hrefclk t s_sync t h_sync sync_i refcl k data figure 84. input data port timing, data referenced to refclk, f dacclk = f refclk note that even though the setup and hold times of sync_i are relative to refclk, the sync_i input is sampled at the internal dacclk rate. in the case where the pll is employed, sync_i must be asserted to meet the setup time with respect to refclk (t s_sync ), but cannot be asserted prior to the previous rising edge of the internal sync_i sample clock. in other words, the sync_i assert edge has to be placed between its successive keep out windows that replicate at the dacclk rate, not the refclk rate. the valid window for asserting sync_i is shaded gray in figure 85 for the case where the pll provides a dacclk frequency of four times the refclk frequency. thus, the minimum setup time is t s_sync , and the maximum setup time is t dacclk ? t h_sync . t srefclk t dacclk t h_sync t s_sync t hrefclk 06452-310 dacclk data sync_i refclk figure 85. input data port timing, data referenced to refclk, f dacclk = f refclk 4 more details of the synchronization circuitry are found in the device synchronization section of this data sheet. table 28. data timing spec ifications vs. temperature timing parameter temperature pll disabled pll enabled min t s (ns) min t h (ns) min kow (ns) min t s (ns) min t h (ns) min kow (ns) data with respect to refclk ?40c ?0.80 3.35 2.55 ?0.83 3.87 2.99 +25c ?1.00 3.50 2.50 ?1.06 4.04 2.98 +85c ?1.10 3.80 2.70 ?1.19 4.37 3.16 ?40c to +85c ?0.80 3.80 3.00 ?0.83 4.37 3.54 data with respect to dataclk ?40c 2.50 ?0.05 2.45 2.50 ?0.05 2.45 +25c 2.70 ?0.20 2.50 2.70 ?0.20 2.50 +85c 3.00 ?0.40 2.60 3.00 ?0.40 2.60 ?40c to +85c 3.00 ?0.05 2.95 3.00 ?0.05 2.95 sync_i to refclk ?40c 0.30 0.65 0.95 0.27 1.17 1.39 +25c 0.25 0.75 1.00 0.19 1.29 1.48 +85c 0.15 0.90 1.05 0.06 1.47 1.51 ?40c to +85c 0.30 0.90 1.20 0.27 1.47 1.74
ad9776a/ad9778a/AD9779A rev. b | page 48 of 56 optimizing the data input timing the ad9776a/ad9778a/AD9779A have on-chip circuitry that enables the user to optimize the input data timing by adjusting the relationship between the dataclk output and dclk_smp (the internal clock that samples the input data). this optimization is made by a sequence of 3-wire interface register read and write operations. the timing optimization can be done under strict control of the user, or the device can be programmed to maintain a configurable timing margin automatically. this function is only available when the input data is referenced to the dataclk output. each of these methods is detailed in the following section. figure 86 shows the circuitry that detects sample timing errors and adjusts the data interface timing. the dclk_smp signal is the internal clock used to latch the input data. ultimately, it is the rising edge of this signal th at needs to be centered in the valid sampling period of the input data. this is accomplished by adjusting the time delay, t d , which changes the dataclk timing and, as a result, the arrival time of the input data with respect to dclk_smp. timing error irq d q q d clk clk dclk_smp pd1[0] t m t d t m dataclk delay[3:0] timing margin[3:0] dataclk timing error type timing error detection 06452-402 figure 86. timing error detection and optimization circuitry the error detect circuitry works by creating two sets of sampled data (referred to as the margin test data) in addition to the actual sampled data used in the device data path. one set of sampled data is latched before the actual data sampling point. the other set of sampled data is latched after the actual data sampling point. if the margin test data match the actual data, the sampling is considered valid and no error is declared. if there is a mismatch between the actual data and the margin test data, an error is declared. the data timing margin[3:0] variable determines how much before and after the actual data sampling point the margin test data are latched. therefore, the data timing margin variable determines how much setup and hold margin the interface needs for the data timing error irq to remain inactive (show error free operation). therefore, the timing error irq is set whenever the setup and hold margins drop below the data timing margin[3:0] value and does not necessarily indicate that the data latched into the device is incorrect. in addition to setting the data timing error irq, the data timing error type bit is indicated when an error occurs. the data timing error type bit is set low to indicate a hold error and high to indicate a setup error. figure 87 shows a timing diagram of the data interface and the status of the data timing error type bit. t m t m data timing error = 0 t m t m data timing error = 1 data timing error type = 1 t m t m data delayed data sampling actual sampling instant delayed clock sampling timing error = 1 data timing error type = 0 06452-403 figure 87. timing diagram of margin test data automatic timing optimization when automatic timing optimization mode is enabled (register 0x03, bit 7 = 1), the device continuously monitors the data timing error irq and data timing error type bits. the dataclk delay[3:0] is increased if a setup error is detected and decreased if a hold error is detected. the value of the dataclk delay[3:0] setting currently in use can be read back by the user. manual timing optimization when the device is operating in manual timing optimization mode (register 0x03, bit 7 = 0), the device does not alter the dataclk delay[3:0] value from what is programmed by the user. by default, the dataclk delay enable bit is inactive. this bit must be set high for the dataclk delay[3:0] value to be realized. the delay (in absolute time) when programming dataclk delay between 00000 and 11111 varies from about 700 ps to about 6.5 ns. the typical delays per increment over temperature are shown in table 29 . table 29. data delay line typi cal delays over temperature delay ?40c +25c +85c unit zero code delay (delay upon enabling delay line) 630 700 740 ps average unit delay 175 190 210 ps when the device is placed into manual mode, the error checking logic is activated. if the irqs are enabled, an interrupt is generated if a setup/hold violation is detected. one error check operation is performed per device configuration. any change to the data timing margin[3:0] or dataclk delay[3:0] values triggers a new error check operation.
ad9776a/ad9778a/AD9779A rev. b | page 49 of 56 device synchronization system demands can impose two different requirements for synchronization. some systems require multiple dacs to be synchronized to each other. this is the case when supporting transmit diversity or beam forming, where multiple antennas are used to transmit a correlated signal. in this case, the dac outputs need to be phase aligned with each other, but there may not be a requirement for the dac outputs to be aligned with a system level reference clock. in systems with a time division multiplexing transmit chain, one or more dacs may need to be synchronized with a system level reference clock. the options for synchronizing devices under these two conditions are described in the synchronization logic overview section and the synchronizing devices to a system clock section. synchronization logic overview figure 88 shows the block diagram of the on-chip synchroniza- tion logic. the basic operation of the synchronization logic is to generate a single dacclk-cycle-wide initialization pulse that sets the clock generation state machine logic to a known state. this initialization pulse loads the clock generation state machine with the clock state[4:0] value as its next state. if the initializa- tion pulse from the synchronization logic is generated properly, it is active for one dacclk cycle, every 32 dacclk cycles. because the clock generation state machine has 32 states operating at the dacclk rate, every initialization pulse received after the first pulse loads the state in which the state machine is already in, maintaining proper clocking operation of the device. sync delay pulse generation logic error detect circuitry clock generation state machine dacclk bit 0 (1 interpolation) bit 1 (2) bit 2 (4) bit 3 (8) bit 4 (8 with zero stuffing) mux sync irq sync_i delay register (reg 0x0, bits [ 7:4 ]) refclk internal pll pll bypass 06452-094 load dacclk offset value (reg 0x07, bits[4:0]), one dacclk cycle/increment f sync_1 < f data /2^n figure 88. synchronization circuitry block diagram nominally, the sync_i input should have one rising edge every 32 clock cycles (or multiple of 32 clock cycles) to maintain proper synchronization. the pulse generation logic can be programmed to suppress outgoing pulses if the incoming sync_i frequency is greater than dacclk/32. extra pulses can be suppressed by the ratios listed in table 30 . the sync_i frequency can be lower than dacclk/32 as long as output pulses are generated from the pulse generation circuit on a multiple of 32 dacclk periods. in any case, the maximum frequency of sync_i must be less than f dataclk . table 30. settings required to support various sync_i frequencies sync_i ratio[2:0] sync_i rising edges required for synchronization pulse 000 1 (default) 001 2 010 4 011 8 100 16 101 invalid setting 110 invalid setting 111 invalid setting as an example, if a sync_i signal with a frequency of f dacclk /4 is used, then both 011 and 100 are valid settings for the sync_i ratio[2:0] value. a setting of 011 results in one initialization pulse being generated every 32 dacclk cycles, and a setting of 100 results in one initialization pulse being generated every 64 dacclk cycles. both cases result in proper device synchronization. the clock state[4:0] value is the state to which the clock generation state machine resets upon initialization. by varying this value, the timing of the internal clocks with respect to the sync_i signal can be adjusted. every increment of the clock state[4:0] value advances the internal clocks by one dacclk period. synchronization timing error detection the synchronization logic has error detection circuitry similar to the input data timing. the sync_i timing margin[3:0] variable determines how much setup and hold margin the synchronization interface needs for the sync timing error irq bit to remain inactive (that is, to indicate error free operation). therefore, the sync timing error irq bit is set whenever the setup and hold margins drop below the sync_i timing margin[3:0] value and, therefore, does not necessarily indicate that the sync_i input was latched incorrectly. when the sync timing error irq bit is set, corrective action can be taken to restore timing margin. one course of action is to temporarily reduce the timing margin until the sync timing error irq is cleared. then, increase the sync_i delay by two increments and check whether the timing margin has increased or decreased. if it has increased, continue incrementing the value of sync_i delay until the margin is maximized. however, if incrementing the sync_i delay reduced the timing margin, then the delay should be reduced until the timing margin is optimized.
ad9776a/ad9778a/AD9779A rev. b | page 50 of 56 synchronizing devices to a system clock the ad9776a/ad9778a/ad 9779a offer a pulse mode synchro- nization scheme (see figure 89 ) to align the dac outputs of multiple devices within a system to the same dacclk edge. the internal clocks are synchronized by providing either a one- time pulse or a periodic signal to the sync_i inputs (sync_i+, sync_i?). the sync_i signal is sampled by the internal dacclk sample rate clock. the sync_i input frequency has the following constraint: f sync_i f data when the internal clocks are synchronized, the data-sampling clocks between all devices are phase aligned. the data input timing relationships can be referenced to either refclk or dataclk. for this synchronization scheme, all devices are slave devices, and the system clock generation/distribution chip serves as the master. it is vital that the sync_i signal be distributed between the dacs with low skew. likewise, the refclk signals must be distributed with low skew. any skew on these signals between the dacs must be accounted for in the timing budget. figure 89 shows an example clock and synchronization input scheme. figure 90 shows the timing of the sync_i input with respect to the refclk input. note that although the timing is relative to the refclk signal, sync_i is sampled at the dacclk rate. this means that the rising edge of the sync_i signal must occur after the hold time of the preceding dacclk rising edge, not the preceding refclk rising edge. interrupt request operation the irq pin (pin 71) acts as an alert in the event that the device has a timing error and should be queried (by reading register 0x19) to determine the exact fault condition. the irq pin is an open-drain, active low output. the irq pin should be pulled high external to the device. this pin can be tied to the irq pins of other devices with open-drain outputs to wire-or these pins together. there are two different error flags that can trigger an interrupt request: a data timing error flag or a sync timing error flag. by default, when either or both of these error flags are set, the irq pin is active low. either or both of these error flags can be masked to prevent them from activating an interrupt on the irq pin. the error flags are latched and remain active until the interrupt register, register 0x19, is either read from or the error flag bits are overwritten. system clock low skew clock driver low skew clock driver matched length traces refclk sync_i refclk sync_i ou t ou t m a tched length traces pulse generator 06452-311 figure 89. multichip synchronization in pulse mode dacclk refclk sync_i t s_sync t h_sync 06452-312 figure 90. timing diagram of sync_i with respect to re fclk when synchronizing multiple devices to each other
ad9776a/ad9778a/AD9779A rev. b | page 51 of 56 power dissipation figure 91 to figure 99 show the power dissipation of the 1.8 v and 3.3 v digital and clock supplies in single dac mode and dual dac mode. in addition to this, the power dissipation/current of the 3.3 v analog supply (mode and speed independent) in single dac mode is 102 mw/31 ma. in dual dac mode, this is 182 mw/55 ma. when the p ll is enabled, it adds 50 ma/90 mw to the 1.8 v clock supply. 0 0 250 f data (msps) power (w) 0.6 0.7 0.5 0.4 0.3 0.2 0.1 25 50 75 100 125 150 175 200 225 8 interpolation, zero stuffing 8 interpolation 4 interpolation 4 interpolation, zero stuffing 2 interpolation 1 interpolation 2 interpolation, zero stuffing 1 interpolation, zero stuffing 06452-076 figure 91. total power dissipation, i data only, real mode 0 0 250 f data (msps) power (w) 0.4 25 50 75 100 125 150 175 200 225 8 interpolation 4 interpolation 2 interpolation 1 interpolation 0.3 0.2 0.1 06452-078 figure 92. power dissipation, digital 1. 8 v supply, i data only, real mode, does not include zero stuffing 0 0 250 f data (msps) power (w) 0.08 25 50 75 100 125 150 175 200 225 8 interpolation 4 interpolation 2 interpolation 1 interpolation 0.06 0.04 0.02 06452-079 figure 93. power dissipati on, clock 1.8 v supply, i data only, real mode, includes modulation modes, does not include zero stuffing 0 0 250 f data (msps) power (w) 0.075 25 50 75 100 125 150 175 200 225 0.050 0.025 all interpolation modes 06452-080 figure 94. power dissipation, digital 3. 3 v supply, i data only, real mode, includes modulation mo des and zero stuffing 0 0 300 250 275 f data (msps) power (w) 0.6 1.0 0.7 0.8 0.9 0.5 0.4 0.3 0.2 0.1 25 50 75 100 125 150 175 200 225 1 interpolation 1 interpolation, zero stuffing 2 interpolation, all modulation modes 2 interpolation, zero stuffing 4 interpolation, all modulation modes 4 interpolation, zero stuffing 8 interpolation, all modulation modes 8 interpolation, zero stuffing 06452-077 figure 95. total power dissipation, dual dac mode 0 0 250 f data (msps) power (w) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 25 50 75 100 125 150 175 200 225 2 interpolation 4 interpolation 1 interpolation, no modulation 8 interpolation, f dac /8, f dac /4, f dac /2, no modulation 06452-081 figure 96. power dissipati on, digital 1.8 v supply, i and q data, dual dac mode, does not include zero stuffing
ad9776a/ad9778a/AD9779A rev. b | page 52 of 56 0 0 250 f data (msps) power (w) 0.125 25 50 75 100 125 150 175 200 225 2 interpolation 4 interpolation 1 interpolation, no modulation 8 interpolation, f dac /8, f dac /4, f dac /2, no modulation 0.100 0.075 0.050 0.025 06452-082 figure 97. power dissipati on, clock 1.8 v supply, i and q data, dual dac mode, does not include zero stuffing 0 0 250 f data (msps) power (w) 0.075 25 50 75 100 125 150 175 200 225 0.050 0.025 all interpolation modes 06452-083 figure 98. power dissipa tion, digital 3.3 v supply, i and q data, dual dac mode 0.16 0 0 1200 f dac (msps) power (w) 0.14 0.12 0.10 0.08 0.06 0.04 0.02 200 400 600 800 1000 06452-084 figure 99. dvdd18 power dissipation of inverse sinc filter power-down and sleep modes the ad9776a/ad9778a/AD9779A have a variety of power-down modes; thus, the digital engine, main txdacs, or auxiliary dacs can be powered down individually or together. via the 3-wire interface port, the main txdacs can be placed in sleep or power- down mode. in sleep mode, the txdac output is turned off, thus reducing power dissipation. the reference remains powered on, however, so that recovery from sleep mode is very fast. with the power-down mode bit set (register 0x00, bit 4), all analog and digital circuitry, including the reference, is powered down. the 3-wire interface port remains active in this mode. this mode offers more substantial power savings than sleep mode, but the turn-on time is much longer. the auxiliary dacs also have the capability to be programmed into sleep mode via the 3-wire interface port. the auto power-down enable bit (register 0x00, bit 3) controls the power-down function for the digital section of the devices. the auto power-down function works in conjunction with the txenable pin (pin 39); see table 31 for details. table 31. txenable (pin 39) description 0 if auto power-down enable bit = 0, flush data path with 0s. if auto power-down enable bit = 1, flush data for multiple refclk cycles; then, automatically place the digital engine in power-down state. dacs, reference, and 3-wire interface port are not affected. 1 normal operation.
ad9776a/ad9778a/AD9779A rev. b | page 53 of 56 evaluation board overview evaluation board operation the ad9776a/ad9778a/AD9779A evaluation board is provided to help users quickly become familiar with the operation of the device and to evaluate the device performance. to operate the evaluation board, the user needs a pc, a 5 v power supply, a clock source, and a digital data source. the user also needs a spectrum analyzer or an oscilloscope to observe the dac output. the typical evaluation setup is shown in figure 100 . a sine or square wave clock can be used to source the dac sample clock. the spectral purity of the clock directly affects the device per- formance. a low noise, low jitter clock source is required. all necessary connections to the evaluation board are shown in more detail in figure 101 . digital pattern generator adapter cables clock generator ad9776a/ ad9778a/ AD9779A evaluation board clkin spi port dataclk out c lock in spectrum analyzer 1.8v power supply 3.3v power supply 0 6452-097 figure 100. typical test setup spi port AD9779A j1 clock in p4 digital input connector s7 dclkout dvdd18 dvdd33 cvdd18 avdd33 j2 5v supply analog devices ad9776a/ ad9778a/ AD9779A s5 output 1 s6 output 2 adl537x local osc input modulator output +5v gnd jp4 jp15 jp8 jp14 jp3 jp16 jp2 jp17 06452-095 figure 101. ad9776a/ad9778a/AD9779A evaluation board showing all connections
ad9776a/ad9778a/AD9779A rev. b | page 54 of 56 the evaluation board comes with software that allows the user to program the on-chip configuration registers. via the 3-wire interface port, the devices can be programmed into any of its various operating modes. the default software window is shown in figure 102 . the evaluation board also comes populated with the adl537x modulator to allow for the evaluation of an rf subsystem. complete details on the evaluation board and the 3-wire interface software can be downloaded from the analog devices website. 1. set interpolation rate 2. set interpolation filter mode 3. set input data format 4. set dataclk polarity to match input timing 0 6452-099 figure 102. 3-wire interface port software window
ad9776a/ad9778a/AD9779A rev. b | page 55 of 56 outline dimensions compliant to jedec standards ms-026-aed-hdt 1 25 26 50 76 100 75 51 14.00 bsc sq 16.00 bsc sq 0.27 0.22 0.17 0.50 bsc 1.05 1.00 0.95 0.15 0.05 0.75 0.60 0.45 seating plane 1.20 max 1 25 26 50 76 100 75 51 6.50 nom 7 3.5 0 coplanarity 0.08 0.20 0.09 top view (pins down) bottom view (pins up) conductive heat sink pin 1 072408-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 103. 100-lead thin quad flat package, exposed pad [tqfp_ep] (sv-100-1) dimensions shown in millimeters ordering guide model temperature range package description package option ad9776absvz 1 ?40c to +85c 100-lead thin quad flat package, exposed pad [tqfp_ep] sv-100-1 ad9776absvzrl 1 ?40c to +85c 100-lead thin quad flat package, exposed pad [tqfp_ep] sv-100-1 ad9778absvz 1 ?40c to +85c 100-lead thin quad flat package, exposed pad [tqfp_ep] sv-100-1 ad9778absvzrl 1 ?40c to +85c 100-lead thin quad flat package, exposed pad [tqfp_ep] sv-100-1 AD9779Absvz 1 ?40c to +85c 100-lead thin quad flat package, exposed pad [tqfp_ep] sv-100-1 AD9779Absvzrl 1 ?40c to +85c 100-lead thin quad flat package, exposed pad [tqfp_ep] sv-100-1 ad9776a-ebz 1 evaluation board ad9778a-ebz 1 evaluation board AD9779A-ebz 1 evaluation board 1 z = rohs compliant part.
ad9776a/ad9778a/AD9779A rev. b | page 56 of 56 notes ?2007C2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06452-0-9/08(b)

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